Chinese chips
  • Global layout and capacity inventory of semiconductor wafer fabs
    Global layout and capacity inventory of semiconductor wafer fabs
      ST: Establishing joint venture wafer fabs in China+collaborating with Chinese wafer foundries ST's SiC wafers and STM32 MCUs both adopt a dual supply chain strategy. For SiC wafers, ST is laying out production capacity through joint ventures with local enterprises. ST and Sanan Optoelectronics have jointly established Anyifa Semiconductor in Chongqing, China. The joint venture factory plans to have an annual production capacity of 480000 8-inch silicon carbide wafers, mainly producing automotive grade electronic control chips. The joint venture factory adopts ST's SiC patented manufacturing process technology and selects locally produced SiC substrates in China. The packaging and testing of SiC devices are completed by STMicroelectronics Shenzhen Saiyifa, forming a complete localized 8-inch SiC supply chain in China. For STM32 MCU, ST has chosen to cooperate with local wafer foundries. In November 2024, ST announced that it had commissioned Huahong to manufacture STM32 MCUs and other products with 40nm nodes in China to achieve localization of STM32. On this basis, ST's STM32 MCU can provide fully localized supply chain support for global OEM manufacturers operating in China, as well as supply chain options for Chinese OEM manufacturers operating internationally. For gallium nitride (GaN) business. ST announced in March 2025 that it had signed a GaN technology development and manufacturing agreement with 8-inch silicon-based GaN manufacturer Innolux to collaborate on a joint development plan for GaN power technology. Based on a flexible supply chain layout, both parties will expand their respective GaN product portfolios and market supply capabilities, effectively enhancing supply chain resilience. ·NXP: Establishing a joint venture wafer fab in Singapore to expand its supply chain in China NXP is also actively promoting the strategy of "in China, for China". On the one hand, NXP has established a joint venture, VSMC, with world leading companies in Singapore, a tariff friendly region of China; On the other hand, NXP announced in December 2024 that it plans to build a new supply chain in China and bring front-end manufacturing to China's domestic market. The total investment of the VSMC project is approximately 7.8 billion US dollars (60% owned by World Advanced and 40% owned by NXP). VSMC's first 12 inch wafer fab uses 130nm to 40nm technology to produce mixed signal, power management, and analog products, supporting the needs of end markets such as automotive, industrial, consumer electronics, and mobile devices. Last December, Andy Micallef, Executive Vice President of NXP, announced that the company was seeking to expand its supply chain in China to provide services to enterprises that require domestic supply chains in China. NXP stated at the time that it would relocate some of its chip front-end manufacturing to China and was exploring the possibility of establishing cooperation with local wafer foundries. ·Infineon: localizing production of commodity level products in China At the end of last year, Infineon CEO Jochen Hanebeck stated that the company is localizing the production of commodity grade products in China, with the aim of strengthening close ties with customers in the Chinese market. On June 11, 2025, Infineon officially released its localization strategy of "in China, for China". In terms of localized production, Infineon's automotive business has already completed localized mass production of multiple products. The company plans to cover the localization of major products by 2027, including microcontrollers, high and low voltage power devices, analog mixed signals, sensors, and storage devices. In order to better serve the Chinese automotive market and meet the increasing demand for MCUs from Chinese customers, the next generation 28nm TC4x product will be produced locally in China for both front-end and back-end production. ·US semiconductor IDM is also flexibly responding to tariff challenges During the earnings conference call for the first quarter of 2025, Haviv Ilian, CEO of Texas Instruments, stated that the world is currently in a highly uncertain period, with tariffs and geopolitical factors disrupting the global supply chain and causing unpredictable economic conditions; China is not only an important terminal market, but also a key node in the global supply chain. He also emphasized that the company has established a highly flexible supply chain system that can optimize production paths and reduce the impact of tariffs on costs. At present, TI adopts the "dual design" of its internal manufacturing process. For example, part of its embedded processors are produced by Taiwan, China's OEM factory, and the other part is produced by Lee Hai's factory in the United States. In the case of high tariffs between China and the United States, the products delivered by TI to Chinese customers are produced by Taiwan, China OEM. Global layout, process technology, and production capacity distribution of semiconductor IDM The article "Global Layout and Capacity Inventory of Semiconductor Wafers (Part 1)" introduces Foundry's global layout and capacity distribution, with a focus on the global layout and distribution of semiconductor IDMs. The previous article introduced Samsung's situation, so this article will not elaborate further. ·Intel   1.1: Distribution of Intel's global manufacturing bases Image source: Intel official website Intel proposed the "IDM 2.0" strategy in 2021, investing billions of dollars to lay out wafer fabs, attempting to regain the voice of chip manufacturing through a three pronged approach of "self construction+foundry+cooperation". In June 2023, Intel announced at an investor webinar that it had combined its Technology Development (TD), Contract Manufacturing, and IFS departments and required the department to be responsible for its own profits and losses. According to the plan, Intel's foundry business unit (IFS) will achieve breakeven by the end of 2030.   1.2: Intel's global wafer fab layout and process technology. As of late June 2025, Intel operates over 10 wafer fabs in 7 cities worldwide, mainly located in Arizona, Oregon, New Mexico, Ohio in the United States (awaiting mass production), Lexlip in Ireland, Jerusalem in Israel, and Saxony Anhalt in Germany (awaiting mass production); We operate testing plants in six cities worldwide, including Penang and Kulin in Malaysia, Chengdu in China, San Jose in Costa Rica, Ho Chi Minh City in Vietnam, New Mexico in the United States, and Wroc ł aw in Poland (awaiting mass production). ·Texas Instruments   2.1: Layout of Texas Instruments' global wafer fabs and packaging and testing facilities. Source: In recent years, Texas Instruments (TI) has continued to increase its investment in 12 inch (300mm) processes from 45nm to 130nm. The company has invested in the construction of seven new 12 inch (300mm) wafer fabs, which will bring improvements in scale, efficiency, and quality. TI is building a new 12 inch semiconductor wafer manufacturing plant (SM1, SM2, SM3, SM4) in Sherman, Texas, with a total investment of $30 billion. After completion, the plant will produce millions of analog and embedded processing chips per day. Among them, SM1 will be put into operation as early as 2025.   2.2: Texas Instruments Global Wafer Plant Layout and Process Technology In addition to wafer fabs, TI also owns and operates assembly and testing facilities worldwide, achieving regional diversification and controlling the supply chain on this basis. Currently, TI is investing in enhancing its assembly and testing capabilities, and improving the availability of manufacturing processes in multiple locations. TI has closed survey bases in Aguascalientes in Mexico, Kuala Lumpur and Malacca in Malaysia, New Taipei City in Taiwan, China, Baguio City in the Philippines, Clark Free Port District and other cities. It is expected that by 2030, over 95% of the company's wafer manufacturing, assembly, and testing operations will be transferred internally. ·SK Hynix   3.1: SK Hynix has production and manufacturing bases in four cities around the world. Image source: SK Hynix official website SK Hynix was formerly known as Modern Electronics Industry Co., Ltd., established in 1983. After being acquired by SK Group in 2012, it was officially renamed SK Hynix Co., Ltd. SK Hynix is committed to producing semiconductor products primarily consisting of DRAM, NAND Flash, and CIS non memory. Currently, the company has four production bases in Lichuan and Cheongju, South Korea, Wuxi and Chongqing (closed testing factory), China, and sales, research and development bases in 16 countries and regions worldwide.   3.2: SK Hynix Global Wafer Plant Layout and Capacity In recent years, SK Hynix has increased its business profits by building new production lines, renovating production lines, and relocating factories. In terms of new production lines, SK Hynix plans to build four 12 inch wafer fabs in Longin City, Gyeonggi Province, South Korea, forming the Longin Semiconductor Cluster (Phase 1/2/3/4). Phase 1 is scheduled to be completed in May 2027 and will also build a "mini wafer fab" equipped with 300mm wafer processing equipment, providing a research environment for Korean component, material, and equipment suppliers to develop, showcase, and evaluate new technologies. In terms of production line renovation, by the end of February 2025, SK Hynix will complete the renovation of its M10F factory in Licheon City, Gyeonggi Province, South Korea, and transform it into a production base for packaging HBM. The M10F factory adds HBM packaging capacity for 10000 wafers per month, increasing the total production capacity from 120000 wafers to 130000 wafers. It is expected that by the end of 2025, with the commissioning of the M15X factory in Qingzhou City, the total production capacity will reach 160000 to 170000 wafers. In terms of factory relocation, SK Hynix System IC (formerly known as SK Hynix Foundry Business Unit) will relocate its M8 factory located in Cheongju, South Korea to Wuxi, China and rename it for registration before May 2022. M8 factory has a monthly production capacity of 100000 8-inch wafers, producing DDI, PMIC, and CIS. Original M8 factory produces DDI for LG LCD screens, PMIC for Silicon Mitus, and CIS for SK Hynix. SK Hynix also has a packaging and testing factory in Chongqing, China - Aisikai Hynix Semiconductor (Chongqing) Co., Ltd., which mainly produces Nand Flash, a flash memory product suitable for mobile terminals. The product is mainly used in mobile terminal devices such as smartphones, tablets, USB, etc. ·Meiguang   4.1: Micron's global wafer fab layout and production capacity. Micron's headquarters is located in Boise, Idaho, and its wafer fabs are spread across Boise, Idaho in the United States, Taichung in Taiwan, Hiroshima in Japan, and Singapore. According to the news released by Micron in mid June 2025, the company plans to invest $200 billion to support semiconductor manufacturing and research and development in the United States, introducing HBM manufacturing to the domestic market. It is reported that Micron will start building the Boise wafer fab in October 2023 and begin producing DRAM in 2027. Now, the company plans to build a second wafer fab in Boise, expected to be completed and put into operation before the first wafer fab in New York State, and to create synergies with existing production lines. After the completion of the two factories, the HBM packaging project will be launched. Over the past few decades, Micron has also expanded its business through continuous mergers and acquisitions. In 2010, the company acquired Numonyx, a flash chip manufacturer, for $1.27 billion; In 2013, Micron acquired Elpida Memory and expanded its memory business; In 2016, Micron also acquired PC memory manufacturers Rexchip and Innotera Memories; In 2024, Micron acquired AU's wafer fabs in Taichung and Tainan to support its DRAM production business in Taichung and Taoyuan factories. The Hiroshima plant in Japan is a facility that was acquired after the merger with Erbida. By 2025, the Hiroshima plant will produce 1 gamma DRAM, and in addition, it will also produce HBM. According to the plan, Micron will also build a new DRAM chip manufacturing plant in Hiroshima and introduce EUV equipment, with advanced DRAM being mass-produced as early as the end of 2027; Micron Taichung Plant 4 was acquired from AU Optronics, and together with A3 Plant, it forms Micron's vertically integrated DRAM manufacturing base in Taiwan. Based on this, Micron Taichung Plant will increase its monthly wafer production to 60000 pieces by the end of 2025. ·STMicroelectronics   4.2: ST's front-end/back-end factory layout supports global enterprises' multi wafer procurement strategy (information updated as of March 2025) Image source: ST STMicroelectronics' wafer manufacturing plants are mainly concentrated in Europe and Asia, specifically distributed in Norrkoping, Sweden, Crolles, Rousset, Tours in France, Agrate and Catania in Italy, Chongqing, Singapore and other regions in China. In addition, ST also has semiconductor sealing and testing plants in cities such as Rennes in France, Marcianise in Italy, Bouskoura in Morocco, Kirkop in Malta, Shenzhen in China, Muar in Malaysia, and Calamba in the Philippines.   5.1: STMicroelectronics' global wafer fab layout and production capacity. Based on the layout of the front/back processes mentioned above, ST can support global enterprises' multi wafer procurement strategies. For customers who are very concerned about the origin of wafers, ST will prioritize providing wafers from the required origin for these customers; For some customers who are not sensitive to their origin, ST will coordinate the entire global supply chain. Now, ST is actively promoting the upgrade plan of its SiC wafer fab, with the core goal of gradually upgrading the original 6-inch production line to an 8-inch production line starting from Q3 2025. For example, its Catania factory in Italy will transition from 6-inch to 8-inch production processes in Q3 2025; Subsequently, the Singapore factory will also initiate an upgrade to 8-inch SiC wafer production within 2025. This move aims to consolidate its leading position in the rapidly growing high-performance power semiconductor market by improving production efficiency and reducing costs, and to coordinate with its dual supply chain system construction strategy. ·NXP NXP currently has 8 wafer fabs (including 4 planned to close 8-inch fabs). Due to the high cost and outdated technology of 8-inch fabs (all of which are mature processes above 100nm), the company is gradually phasing out 8-inch fabs and shifting towards 12 inch fabs. Among the four 8-inch wafer fabs that NXP will close, one is located in Nijmegen, the Netherlands, and three are located in the United States. After the closure, production capacity will be relocated to the 12 inch production lines of the VSMC and ESMC joint ventures.   5.2: NXP's global wafer fab layout (excluding the planned closure of 4 8-inch wafer fabs) In the future, NXP may reduce to 5 core fabs. In addition, NXP has invested $7.8 billion in its joint venture plant in Singapore (VSMC, planned for mass production in 2027), focusing on 130nm-40nm mixed signal and power management chips, with a monthly production capacity of 55000 wafers by 2029; NXP also has a joint venture wafer fab ESMC in Germany, but it only holds a 10% stake and is operated by TSMC (which holds a 70% stake). The total investment of the fab exceeds 10 billion euros, with a planned monthly production capacity of 40000 12 inch wafers. Construction will begin in the second half of 2024 and production will begin at the end of 2027. ·Infineon   6: Distribution of Infineon's 15 factories (including front-end and back-end factories, data as of September 30, 2024) Image source: Infineon has a total of 15 factories worldwide (including front-end and back-end factories) as of September 30, 2024. Among them, the United States has gathered several production bases of Infineon, with wafer fabs located in Austin, Texas and Mesa, Arizona. At the end of February 2025, the company announced the sale of its 8-inch wafer fab Fab25 located in Austin, Texas, to SkyWater. It is reported that Fab25 focuses on producing 130nm to 65nm basic chips that are crucial for industrial, automotive, and defense applications.   7: Infineon's global wafer fab layout (incomplete statistics). Infineon also has front-end wafer fabs in Kulin Malaysia, Regensburg and Dresden in Germany, and Filach in Austria. Among them, the K3 wafer fab in Kulin, Malaysia is an 8-inch SiC wafer fab. Phase 1 has been put into operation since August 2024, with initial production capacity focused on SiC power semiconductors. It is expected that after Phase 2 is put into operation, the total production capacity will increase to the world's largest scale, covering the production of gallium nitride epitaxy; The Smart Power Fab in Dresden, Germany is the world's first semiconductor factory to comply with Industry 4.0 standards, covering wafer processing, testing, and separation processes; It is planned to start production in 2026 and is expected to reach full capacity production by 2031. ·Ansenmei Figure 6: Anson's manufacturing factories are scattered in 9 countries around the world. Image source: Anson has 19 production factories (including front-end and back-end processes) in 9 countries, located in the United States, Canada, China, Czech Republic, Japan, Malaysia, Philippines, South Korea, and Vietnam. Anson Semiconductor was originally part of Motorola's semiconductor division, spun off from Motorola in 1989, and went public on NASDAQ in 2000. The 6-inch wafer fab in Roznov, Czech Republic, the 6-inch wafer fab/packaging and testing plant in Seremban, Negeri Sembilan, Malaysia, and the packaging and testing plant in Kamona, Krabi Province, Philippines, which are still in operation, are all factories that were spun off from Motorola at that time.   8: Anson's global manufacturing base layout (including wafer fabs and packaging and testing facilities). In addition, most of the wafer fabs/packaging and testing facilities currently operated by Anson are acquired through mergers and acquisitions. Including its 12 inch wafer fab located in East Fishkill, New York, which was acquired in 2019 through the purchase of the Grosvenor Fab10 wafer fab, and its 8-inch wafer fab located in South Par, Iowa, which was acquired in 2014 through the purchase of Aptina Imaging. In addition, its 8-inch wafer fabs located in Gresham, Oregon, Mentintop, Pennsylvania, Shenzhen, Guangdong, China, and Wakamatsu, Japan, as well as its 8-inch/6-inch wafer fabs in Bucheon, Gyeonggi Province, South Korea, and its packaging and testing plants in Tongna, Vietnam, Tarak, Philippines, and Burlington, Ontario, Canada, all came from mergers and acquisitions.  ·ADI Figure 7: ADI Global Manufacturing Base and Supply Chain Network Image Source: ADI's product supply chain is mainly completed through the collaboration of "independent wafer fabs+external foundries". The company has deployed 10 independent factories (including front-end and back-end factories) and 50 supply chain factories worldwide, covering 15 countries or regions. The front-end wafer fabs within ADI lead mature processes (Beaverton, Oregon/Limerick, Ireland, USA), and their advanced process technologies are mainly provided by their foundry partners.   9: ADI's internal manufacturing base layout (including wafer fabs and packaging and testing plants) Overall, ADI's internal factories contribute about 50% of wafer production capacity, 80% of testing capacity, and 20% of packaging capacity. Currently, ADI is expanding its wafer fab capacity through internal investment. It is expected that by the end of 2025, the production capacity of wafer fabs located in the United States and Europe will double - the Beaverton factory in Oregon is renovating an 8-inch wafer fab, increasing its cleanroom area by 25000 square feet and doubling its production capacity; The production area of the Limerick factory in Ireland will be expanded by 15000 square feet, with a threefold increase in production capacity; The Camus factory in Washington state is also expanding its production capacity. Most of the testing work for ADI products is conducted in factories in the Philippines, Malaysia, and Thailand, and the assembly business is outsourced to trusted partners. ADI is expanding its testing facilities in Malaysia and Thailand, and has also expanded its campus in the Philippines. In addition, ADI is cross validating testing processes with external partners to ensure that dual procurement can be conducted when needed. ·Microchip Technology Microchip's hybrid supply chain strategy combines US wafer manufacturing plants with global assembly facilities, fully utilizing internal and external foundries and OSAT manufacturers. With the support of strategic partnerships, this manufacturing ecosystem can optimize the production of high-value markets while balancing cost-effectiveness and reliability. In May 2025, Microchip closed its Fab2 wafer fab in Tempe, Arizona, which has a monthly production capacity of 20000 8-inch wafers (1 μ m-250nm process). Its technology and products will be transferred to Fab4 and Fab5 factories. At the same time, Fab4 and Fab5 factories have laid off employees, and the production capacity of the two wafer fabs has been reduced to below short-term demand levels. After the excess inventory is digested, it will gradually return to demand matching production capacity. Fab4 will still maintain a two-week preparation time for resuming production after the layoffs.   10: Global wafer fab layout and current situation of Microchip Technology. In addition, the company's packaging and testing bases are distributed in the United States (Beverly, Massachusetts; Lawrence and Lowell, Massachusetts; Holly Springs, Pennsylvania; San Jose and Garden Grove, California; Simsbury, Connecticut), France, the United Kingdom, Ireland, Germany, Thailand, the Philippines, and other places.
    - June 24, 2025
  • Wolfspeed announces bankruptcy!
    Wolfspeed announces bankruptcy!
    On June 22, American chip manufacturer Wolfspeed announced that it would file for bankruptcy under a restructuring agreement that would eliminate billions of dollars in debt and give creditors control of the company. Wolfspeed stated that the restructuring plan has received sufficient support from creditors, including semiconductor manufacturer Renesas Electronics and investment firm Apollo Global Management. Wolfspeed stated that it will continue to seek approval from more creditors before filing for bankruptcy under bankruptcy laws. Robert Feurle, CEO of Wolfspeed, stated in a statement: "After evaluating potential options for strengthening our balance sheet and adjusting our capital structure, we have decided to take this strategic move because we believe it will put Wolfspeed in the best position in the future. ”According to its proposal, creditors' debts will be converted into equity, and existing shareholders will receive at least 3% and up to 5% of new shares. These ratios imply higher shareholder losses, but higher than the typical level of most bankruptcy cases. The company hopes to continue trading on the New York Stock Exchange, but acknowledges in a statement that it may delist "for a period of time," and Wolfspeed promises that this process will not affect its commitments to customers and suppliers. Wolfspeed expects to emerge from bankruptcy by the end of September after cutting 70% of its debt (approximately $4.6 billion). At that time, the new shareholders will appoint new members of the board of directors. As of the end of March, Wolfspeed held $1.3 billion in cash, which is a significant amount for a company preparing to apply for bankruptcy protection under bankruptcy law. However, the company will face over $6 billion in debt in the coming years, including payments due in 2026, 2028, 2029, 2030, and 2033. The company has rejected the proposal to restructure next year's debt and instead insists on what Wolfspeed's head of investor relations, Tyler Gronbach, previously called a 'comprehensive solution'. According to its bankruptcy proposal, these debts will be reduced, merged, and postponed - with an earliest maturity date of 2030.
    - June 23, 2025
  • Japanese chip distributors have also begun mergers and acquisitions
    Japanese chip distributors have also begun mergers and acquisitions
    The news of mergers and acquisitions by semiconductor distributors has once again come. Kaga Electronics announced that it will acquire the common stock of Xierong Industries through a public offering of shares (TOB) in May 2025. The TOB acquisition period starts on June 2nd and ends on July 11th. We plan to acquire approximately 2.2 million shares, with a total expected acquisition amount of up to approximately 8.7 billion yen. Kaga Electronics was founded in Tokyo on September 12, 1968. It is a well-known independent comprehensive electronics trading company in Japan and a listed company in the Tokyo Stock Exchange. It focuses on the manufacturing of electronic components, semiconductors, EMS, and information equipment. Proxy brands include Mitsubishi Electric, Renesas, ADI, Omnivision, etc. Kaga Electronics had sales of 547.779 billion yen and operating profit of 23.61 billion yen in the fiscal year of March 2025, making it one of the top five major semiconductor/electronic product distributors in Japan. On the other hand, the sales revenue of Xierong Industry in the fiscal year of March 2025 was 57.79 billion yen, with an operating profit of 974 million yen. After the merger, it will become a distributor with sales exceeding 600 billion yen, but it has not yet reached the scale of 1-341 trillion yen of Macnica Holdings, the current leading electronic distributor in Japan, in the fiscal year of March 2025. At present, the electronic distribution pattern in Japan is dominated by Macnica Holdings, the only company with sales exceeding 1 trillion yen, ranking first. The second tier consists of several companies with sales between 400 billion and 500 billion yen, followed by distributors with sales of 200 billion yen and 100 billion yen. In recent years, the trend of integration between distributors with larger sales scales, or large distributors acquiring small distributors, has been accelerating. About a year ago, Ryoyo Electro (with sales of 129.9 billion yen as of January 2023) merged with Ryosan (with sales of 325.6 billion yen as of March 2023) to form Ryosan Ryoyo Holdings (HD). The background is that with the acceleration of the Internet of Things (IoT) and digital transformation (DX), the rapid use of new technologies has brought significant environmental changes to the industry, and the functions and roles required for electronic distributors are changing, including the impact of intensified competition between companies and geopolitical risks related to mergers and acquisitions with semiconductor manufacturers and other manufacturers. The merger of the two companies will bring good synergies. Ryosan has many customers in the automotive field, while Ryoyo Electro has many customers in the medical field, which is conducive to integrating and expanding the customer base of the two companies. On May 14th of this year, Ryosan Ryoyo Holdings (HD) announced its first annual financial report after the merger, with sales of 359.811 billion yen and operating profit of 8.542 billion yen. The overall group goal set by the company is to achieve sales of 500 billion yen and operating profit of 30 billion yen for the fiscal year ending March 2029. In addition, although the types are slightly different, Kanematsu also acquired Electronics End Materials Corporation, a distributor of semiconductor silicon wafers, in March 2025. Over time, the restructuring of Japanese semiconductor distributors is not a new phenomenon: in 2003, Macnica and Fuji Electronics merged to form Macnica Fuji Electronics HD. In 2007, UKC HD and Vitec HD merged to form Leicester HD. The large number of small and medium-sized enterprises is a prominent feature of Japan's semiconductor distributor industry. Traditionally, there have also been many distributors affiliated with the manufacturer system, which has given rise to unique business practices. Therefore, even if there are significant changes in the external environment, it is often difficult to break the existing inertia, and some distributors are forced to struggle. This situation was particularly evident during the COVID-19 epidemic. Despite the tight global semiconductor supply, there is still a market with smooth circulation, which exposes the weakening purchasing power of Japanese distributors, posing a huge challenge to them. Against the backdrop of rising semiconductor/component prices, rising logistics costs, and foreign distributors entering the Japanese market and strengthening their business layout in Japan, it has become increasingly difficult for a single distributor to continue investing. In order to effectively compete with global suppliers, avoid the situation of "not being able to buy others" and maintain this ability, the integration and restructuring trend of Japanese electronic distributors will continue to be promoted in the future. In 2019, five years ago, Texas Instruments (TI) announced the termination of its exclusive distribution agreements with its sales partners, including Marubeni, Avnet, and WPG. This news caused a huge shock in the distributor industry. In addition, mergers and acquisitions by chip manufacturers may also be an important reason for the restructuring of Japanese chip distribution companies. Renesas Electronics acquired Intersil Corporation in 2005 and IDT Corporation in 2007. Since 2008, there has been a trend of termination of distribution agreements between Renesas Electronics and semiconductor trading companies, such as the termination of distribution agreements with RYODEN Corporation (formerly known as Ryoden Shoji Corporation) at the end of February 2011. The role of Japanese distributors in the entire industrial chain is being questioned and reviewed again after the transformation of semiconductor supplier sales strategy and the structural change of the supply chain brought about by the COVID-19 epidemic.
    - June 21, 2025
  • Micron officially confirmed that DDR4 will be discontinued
    Micron officially confirmed that DDR4 will be discontinued
    Due to original manufacturers such as Samsung and Micron locking in the DDR5 and HBM markets, they will gradually stop supplying DDR4, which has led to a surge in DRAM stocking, especially with a significant increase in DDR4 prices. Micron officially confirmed that DDR4 will be discontinued. Last week, Micron confirmed that it has sent a letter to customers notifying them that DDR4 will be discontinued (EOL, End of Life), and it is expected to gradually stop shipping in the next 2-3 quarters. Sumit Sadana, Executive Vice President and Chief Commercial Officer of Micron, stated that DDR4 will continue to be severely out of stock. Sadana stated that the notice of discontinuation of DDR4/LPDDR4 has been handed over to customers recently, mainly targeting the PC and data center fields. It is expected that in the next three quarters, DDR4 DRAM for consumer, PC, and data center use will undergo production reduction or decrease. Future Micron DDR4/LPDDR4 DRAM is mainly provided to long-term cooperative customers in the automotive, industrial, and network industries. In February this year, it was reported that Micron, Samsung, and SK Hynix may stop producing DDR3 and DDR4 memory by the end of this year. In April, it was reported that Samsung notified PC manufacturers that DDR4 would be discontinued by the end of this year, with the final order date set for June. After the news of frequent price increases and factory shutdowns of storage products spread, it triggered a chain reaction in the DRAM market, leading to a surge in inventory. According to a report by Jibang Consulting, after the original factory announced EOL (termination of production), buyers rushed to replenish inventory, causing tight supply in the pellet spot market from April to May and a significant increase in prices. In June, the trend of storage product price increases has not stopped. According to the sales manager of a leading storage module manufacturer in Shenzhen, some DRAM products have recently experienced price increases, mainly DDR4 and DDR3. Some have risen by 100% during this period, while others have risen by 50% within a month. This month's increase is very significant. ”The supply of goods in the spot market is also scarce. According to the Science and Technology Innovation Board Daily, reporters inquired with multiple stores in Huaqiang North about a DDR4 3600MHz 16GB bare strip as the entry point, and the general feedback was "out of stock", indicating that this specification has experienced a shortage of stock on the channel end. Continuously inquiring about memory modules with multiple frequency and capacity specifications, the response received was almost always' out of stock '. Multiple Huaqiangbei merchants have provided feedback that DDR4 prices have recently increased significantly and are accompanied by a shortage of spot goods, while DDR5 prices are relatively stable. SSDs have already experienced a slight increase in prices and are currently stable. The flash memory market also shows that DDR4 memory modules have the strongest upward trend, with some products experiencing a cumulative price increase of over 30% in just two weeks. The price of low capacity eMMC has not only doubled compared to the end of last year, but 16GB/32GB/64GB eMMC has basically the same price. With the decreasing supply of MLC NAND, it will accelerate the further upgrading of storage capacity for application terminals such as TV/security/POS machines in the future. The flash memory market is expected to continue the price increase trend of DDR4 and DDR5 servers in Q3, but the increase will narrow and may fall within the range of 10% -15%. The expected price of DDR5 server products in the third quarter is expected to increase slightly compared to the second quarter, while in the fourth quarter, with the ramp up of original DDR5 production capacity and the improvement of yield, the supply side will concentrate on releasing production capacity, and server DDR5 products will face price fluctuations.
    - June 17, 2025
  • Purchased chip empire?
    Purchased chip empire?
    In the semiconductor world, some companies rely on technology to make a living, while others rely on patents to make a living. Qualcomm, on the basis of possessing these two, has built a chip empire through targeted "buying and buying". Today, Qualcomm is a chip giant spanning mobile phones, automobiles, the Internet of Things, and AI edge computing. But you may not know that the foundation of this empire is the technology teams and assets that have been quietly swallowed, polished with time and patience. GPU: Adreno Rising from the Afterglow of ATI The graphics processing capability of mobile devices in 2006 can be considered "primitive". At that time, the concept of smartphones had not yet become popular, with BlackBerry and Palm Pilot still dominating the market, and the release of the iPhone had to wait until 2007. In this era of mobile graphics processing where 'running a snake is enough', the vast majority of device manufacturers have extremely limited demand for GPUs, focusing more on basic 2D interface rendering and simple multimedia playback functions. However, it is during this seemingly calm period that a far-reaching technology acquisition is brewing. AMD has decided to acquire ATI Technologies for a sky high price of $5.4 billion in order to gain a graphics processing advantage in competition with Intel. This transaction not only changed the landscape of the PC graphics card market, but also unexpectedly planted an important seed for the mobile graphics processing field. In the AMD-ATI acquisition, AMD's main target was ATI's desktop and server GPU business, while ATI's mobile graphics division was considered a "peripheral" at the time. Although this department has considerable technical strength, the market prospects were not clear at the time. The graphics demand for mobile devices is limited, and the entire industry generally lacks confidence in the development potential of mobile GPUs. However, Qualcomm has demonstrated a forward-looking strategic vision. This company, which started with communication chips, is keenly aware that with the continuous enrichment of mobile device functions, graphics processing capabilities will become one of the core competitiveness of future mobile platforms. When AMD sold ATI's mobile GPU division as a "bundle", Qualcomm was quick witted and quickly acquired this experienced team at a relatively low price. After the acquisition, Qualcomm gave this newly acquired GPU division a memorable name: Adreno. This name is not randomly chosen, but rather a letter rearrangement and combination of ATI's famous GPU brand "Radeon". This naming convention not only reflects respect for ATI's technological heritage, but also symbolizes the team's fresh start under its new owner. The name Adreno itself carries a profound technical background. The Radeon series GPU once competed with NVIDIA's GeForce series in the PC field, with a deep accumulation of graphics processing technology. By preserving the symbolic expression of this technological DNA, Qualcomm is actually declaring to the market that Adreno will continue ATI's technological advantages in the field of graphics processing and further develop them. The original team from ATI has brought valuable technological assets to Adreno. These engineers not only have extensive experience in GPU architecture design, but more importantly, they have a deep understanding of various aspects of the graphics rendering pipeline, from vertex processing to pixel shading, from texture mapping to anti aliasing techniques. With the advent of the smartphone era, Adreno has ushered in its own shining moment. Qualcomm has deeply integrated Adreno into the Snapdragon system on chip platform, forming a collaborative optimization of components such as CPU, GPU, DSP, and modem. This SoC design concept not only improves overall performance, but more importantly achieves better power control and thermal management. The development history of Adreno series GPUs can be seen as a microcosm of the progress in mobile graphics processing technology. From the early Adreno 200 series to the current Adreno 740 series, each generation of products has achieved significant improvements in performance, power consumption, and feature support. Especially in terms of support for graphics APIs such as OpenGL ES, Vulkan, DirectX, Adreno has always maintained an industry-leading level. Today, Adreno has far exceeded the technological scope of ATI's mobile GPU. Modern Adreno GPUs not only support traditional 3D graphics rendering, but also integrate cutting-edge technologies such as machine learning acceleration, computational shaders, and variable rate shading (VRS). Adreno has demonstrated strong adaptability and scalability in emerging fields such as AR/VR applications, computational photography, and AI image processing. From a small team in the ATI laboratory to the graphics processing engine that supports billions of mobile devices worldwide today, Adreno's story can be considered a legend in the history of technology. The spark left by ATI, under the careful cultivation of Qualcomm, ultimately ignited the entire sky of mobile graphics processing. CPU: The confidence to invest in self-developed cores In the world of chip design, there is an unwritten rule: when giants start to feel threatened, real change is about to begin. In 2020, when Apple released the MacBook with the M1 chip, the entire industry was shocked. This is not only because M1's performance is stunning, but more importantly, it has proven a truth to the world: based on mobile chips, it is entirely possible to create products that can rival or even surpass traditional x86 processors. In this shock, the one who felt the deepest was none other than Qualcomm. As the dominant player in the field of mobile chips, Qualcomm suddenly found itself facing unprecedented challenges. Apple is no longer satisfied with dominating only in the fields of smartphones and tablets, but has extended its tentacles to the PC market - a field that Qualcomm has always wanted to enter but has never succeeded in breaking through. For a long time, Qualcomm's Snapdragon processors have relied on the Cortex series public core provided by Arm. This model was indeed effective in the early development stages of the mobile market: Arm was responsible for providing mature and stable architecture design, while Qualcomm and other vendors focused on system level optimization and integration. This division of labor cooperation has enabled the rapid development of the Android ecosystem and also contributed to Qualcomm's leadership position in the mobile chip field. However, as the demand for mobile computing continues to increase, this pattern of relying on public architecture is beginning to expose significant limitations. Firstly, the degree of differentiation is limited. When everyone uses the same CPU core, the differences between products are mainly reflected in the process technology, frequency tuning, and integration of peripheral components. It is difficult to form the architectural advantages of the core. Secondly, the space for performance optimization is limited, and the public architecture must take into account the needs of all authorized vendors, making it difficult to conduct in-depth optimization for specific application scenarios. The most fatal thing is that the success of Apple's M-series chips has shown the industry the enormous potential of self-developed architectures. Apple has achieved breakthroughs not only in performance, but more importantly, in power consumption control through completely autonomous architecture design. The advantage of integrating software and hardware has put unprecedented pressure on manufacturers who rely on public architecture. Faced with the impact of Apple's M-series chips, the entire industry has begun to rethink its architecture strategy. Intel is striving to advance its hybrid architecture design, AMD is continuously optimizing its Zen series architecture, and within the Arm ecosystem, major vendors are also seeking more autonomy. As a leader in mobile chips, Qualcomm is deeply aware of the urgency of change. There is a consensus within the company that if we continue to rely entirely on Arm's public core, it will not only be difficult to compete with Apple in terms of performance, but more importantly, we will lose our dominant position in the next round of technological competition. Especially in AI computing, edge computing and other emerging fields, the flexibility and optimization space of self-developed architecture will become a decisive advantage. In January 2021, Qualcomm announced its acquisition of Nuvia for $1.3 billion, which caused a huge shock in the industry. For many people, Nuvia is still a relatively unfamiliar name - this two-year-old startup has less than a hundred employees, neither mass-produced products nor mature business models. The valuation of $1.3 billion was indeed astonishing at the time. However, Qualcomm is not interested in the current situation of Nuvia, but in its technological strength and development potential behind it. The founding team of Nuvia can be described as luxurious: CEO Gerard Williams III was once the chief architect of Apple's A-series chips, involved in the design of multiple generations of processors from A7 to A12X; CTO Manu Gulati and Chief System Architect John Bruno also have extensive experience in designing high-performance processors. This team not only deeply participated in the golden age of Apple chips, but more importantly, they have a unique understanding of how to create high-performance low-power processors. Nuvia's technological roadmap is also highly aligned with Qualcomm's strategic goals. This company focuses on the development of high-performance Arm processors for data center and edge computing, and its design philosophy emphasizes to achieve maximum performance output while maintaining low power consumption. Although the company has not been established for a long time, its technical team has demonstrated impressive design capabilities in a short period of time. More importantly, Nuvia has complete self-developed CPU core design capabilities. From optimizing instruction set architecture, to innovating microarchitecture, to developing compilers and software stacks, Nuvia possesses full stack technical capabilities. This is exactly the core capability that Qualcomm urgently needs. After the acquisition, Qualcomm did not rush to quickly productize Nuvia's technology, but chose a more secure strategy of deep integration. The core technology team of Nuvia has been fully integrated into Qualcomm's research and development system, becoming an important component of Qualcomm's CPU design department. This integration is not just about merging personnel, but also a deep integration of technical concepts and design methodologies. During the integration process, Qualcomm demonstrated considerable patience and strategic determination. The company did not rush to launch transitional products, but gave the Nuvia team sufficient time and resources to steadily advance according to the established technology roadmap. At the same time, Qualcomm will also combine its rich experience in the field of mobile chips, including knowledge in power management, thermal design, manufacturing processes, etc., with Nuvia's high-performance design philosophy. On the basis of Nuvia technology, Qualcomm has begun to re plan its high-performance CPU core development roadmap. This is not only a technical adjustment, but also a significant transformation of the entire product strategy. The new development roadmap places greater emphasis on balancing and optimizing performance and power consumption. Drawing on Nuvia's experience in high-performance processor design, Qualcomm has begun exploring more radical architectural innovations, including wider execution units, deeper pipelines, and smarter branch prediction. At the same time, based on Qualcomm's experience in power control in the field of mobile chips, the new architecture design also pays more attention to dynamic power management under different workloads. In terms of application scenarios, the new roadmap also reflects stronger targeting. In addition to traditional mobile applications, emerging scenarios such as PC computing, edge AI, and cloud native applications have become key optimization targets. This multi scenario optimization strategy provides technical support for Qualcomm's expansion in different markets. In 2024, Qualcomm officially released the Oryon CPU core based on Nuvia technology, marking the first significant achievement in the three-year acquisition of Nuvia. The release of Oryon not only marks Qualcomm's official entry into the era of self-developed CPU cores, but more importantly, injects new vitality into the entire Arm ecosystem. From the technical specifications, the Oryon CPU has indeed demonstrated impressive performance. While maintaining relatively low power consumption, Oryon's single core and multi-core performance have reached industry-leading levels. Especially in terms of AI workloads, Oryon has achieved significant performance improvements through specialized optimization design. The impressive performance of the Oryon CPU is attributed to its innovative breakthroughs in multiple technological aspects. These innovations not only demonstrate the technical strength of the Nuvia team, but also showcase Qualcomm's profound expertise in system level optimization. In terms of microarchitecture design, Oryon adopts a wider execution engine and a deeper out of order execution queue, which can better explore instruction level parallelism. Meanwhile, Oryon has made significant progress in reducing memory access latency through improved branch prediction algorithms and a larger cache hierarchy. In terms of power management, Oryon inherits Qualcomm's rich experience in the field of mobile chips. By finely dividing power domains and dynamically adjusting voltage and frequency, Oryon is able to dynamically adjust power consumption based on actual workloads, maximizing battery life while ensuring performance. In terms of AI acceleration, Oryon integrates specialized matrix operation units and vector processing units, which can efficiently execute various machine learning workloads. This hardware acceleration capability provides strong support for Oryon based devices in AI applications. The launch of the Oryon CPU has also opened up new market opportunities for Qualcomm. The Snapdragon X series processors equipped with Oryon directly target the PC market, competing head-on with Intel and AMD's traditional advantage areas. At the same time, Oryon also provides strong technical support for Qualcomm's layout in emerging markets such as edge computing and AI reasoning. The acquisition price of 1.3 billion US dollars did raise many doubts at the time, but now it seems that the strategic value of this investment has been fully reflected. Nuvia not only brought a world-class CPU design team and core technology to Qualcomm, but more importantly, won the initiative in the next round of technology competition. Wi Fi/Bluetooth: The 'invisible wings' behind Atheros Atheros, once a pioneer in wireless communication, has now become a part of the Qualcomm empire, but its technological DNA still quietly flows through billions of devices. From the initial laptop Wi Fi card to the connection module in today's smartphones, Atheros' technological heritage spans the entire development process of wireless communication era. To understand the value of Atheros, we must return to the starting point of wireless communication technology. In 1998, when the Wi Fi standard was just established and most people were still using dial-up internet, Atheros had already keenly perceived the enormous potential of wireless communication. This company, founded by a research team from Stanford University, has been focused from the beginning on a seemingly simple but extremely complex problem: how to achieve efficient and stable wireless connections between devices. In that era, wireless communication technology was still in its very early stages. The 802.11a/b standard has just been released, with a transmission rate of only 11Mbps and limited connection stability. But Atheros engineers saw the infinite possibilities of this technology and began to delve into various technical aspects such as RF design, antenna technology, signal processing algorithms, etc., attempting to break through the technological bottleneck of wireless communication at that time. The first major breakthrough of Atheros came from the deep optimization of OFDM (Orthogonal Frequency Division Multiplexing) technology. Although this technology has great advantages in theory, it faces many challenges in practical applications, including signal synchronization, inter carrier interference, power consumption control, and other issues. Atheros engineers have successfully solved these technical challenges through innovative algorithm design and hardware optimization, laying the foundation for the rapid development of Wi Fi technology in the future. The key to Atheros standing out in the fierce market competition lies in its continuous investment and breakthroughs in technological innovation. The company has established a development strategy of "technology oriented" since its inception, investing a large amount of resources into the research and development of core technologies. After the release of the 802.11g standard, Atheros was the first to launch a chip solution that supports a transmission rate of 54Mbps, far exceeding its competitors at the time. More importantly, Atheros' chips perform well in power control and signal stability, which enables devices using Atheros chips to provide longer battery life and more reliable connection experience. With the introduction of the 802.11n standard, MIMO (Multiple Input Multiple Output) technology has become an important direction for the development of Wi Fi. Atheros has once again demonstrated its technological innovation capabilities by launching the industry's first commercial chips that support MIMO technology. Through the application of multi antenna technology, Atheros' solution not only significantly improves transmission speed, but also significantly enhances signal coverage and anti-interference capability. During this process, Atheros has accumulated a wealth of RF design experience and signal processing technology. The company's engineers have conducted in-depth research on various complex wireless environments, from residential homes to corporate offices, from dense urban environments to open rural areas, and developed corresponding optimization solutions for different application scenarios. With its strong technical capabilities, Atheros has gradually established its position in the market. The company's first significant breakthrough came from the laptop market. In the era when Wi Fi technology was just emerging, laptops were the most important application carriers, and Atheros, with its excellent chip performance and stability, successfully gained the favor of many laptop manufacturers. With the popularization of home broadband, the consumer router market has begun to develop rapidly. Atheros keenly seized this opportunity and launched a chip solution specifically designed for router applications. These chips not only support higher transmission rates, but also have stronger concurrent processing capabilities, which can provide stable connection services for multiple devices simultaneously. In addition to the consumer market, Atheros has also achieved significant success in the field of enterprise wireless communication. Enterprise level applications have more stringent requirements for wireless communication, and Atheros has launched specialized chip solutions for the enterprise market. These products have reached industry-leading levels in RF performance, concurrent processing capabilities, security encryption, and other aspects. Many enterprise network equipment manufacturers have adopted Atheros' chips to build their enterprise level access points (APs) and wireless controller products. Although Atheros initially started with Wi Fi technology, the company quickly realized that the limitations of a single technology were evident in the field of wireless communication. Different application scenarios require different connectivity technologies, and companies that can provide comprehensive connectivity solutions can gain the greatest advantage in market competition. Based on this understanding, Atheros began to expand into the field of Bluetooth technology. Although Bluetooth technology is not as good as Wi Fi in terms of transmission distance and speed, it has unique advantages in low power consumption and point-to-point connections, making it particularly suitable for applications such as audio transmission and input device connections. Atheros' Bluetooth chip solution also demonstrates excellent technical standards. The company's engineers have conducted in-depth research on various levels of the Bluetooth protocol stack, from the lower level RF design to the upper level application protocols, all of which have been deeply optimized. This enables Atheros' Bluetooth chip not only to have better audio transmission quality, but also to support more device connections and richer application functions. With the rise of smartphones and other mobile devices, modular connectivity solutions have become the mainstream demand in the market. Atheros timely launched a Wi Fi/Bluetooth combination chip, integrating the two technologies into a single chip, which not only reduces costs and power consumption, but also simplifies the design complexity of devices. However, at this time, the entire wireless communication market underwent fundamental changes. The requirements for connecting chips in mobile devices are completely different from those in traditional PC products: smaller size, lower power consumption, higher integration, and stricter cost control. This is undoubtedly a huge challenge for Atheros, which is mainly focused on the PC market. Just as Atheros faced challenges in its transition to the mobile age, Qualcomm emerged. In January 2011, Qualcomm announced the acquisition of Atheros for $3.1 billion, which caused a huge shock in the industry. For many observers, this acquisition price seems too high, especially considering the market challenges faced by Atheros at the time. However, Qualcomm's strategic vision was fully reflected in this acquisition. Qualcomm has a deep understanding of the development trend of the mobile Internet era, and recognizes that connectivity technology will become one of the key elements of mobile device competitiveness. Although Qualcomm has taken a dominant position in the cellular communication field, its strength in non cellular connection technologies such as Wi Fi and Bluetooth is relatively limited. The value of Atheros lies not only in its existing products and market position, but more importantly, its profound technical accumulation and experienced engineering team. Qualcomm values Atheros' core capabilities in RF design, signal processing, protocol stack optimization, and other areas, which complement Qualcomm's cellular communication technology perfectly. In addition, Qualcomm has also seen a trend towards the integration of connectivity technologies. In mobile devices, Wi-Fi、 Multiple connectivity technologies such as Bluetooth and cellular communication need to work together, and manufacturers that can provide unified optimization will have significant competitive advantages. By acquiring Atheros, Qualcomm not only gained world-class connectivity technology, but also laid the foundation for its comprehensive layout in the mobile communication field. After the acquisition, Qualcomm did not simply operate Atheros as an independent business unit, but chose a strategy of deep integration. This integration is not only reflected in the technical aspect, but also in the integration of culture and organizational structure. In terms of technology integration, Qualcomm has deeply integrated Atheros' connectivity technology with its own mobile processor technology. This integration is not simply physical splicing, but collaborative optimization at various levels such as architecture design, power management, and signal processing. Through this deep integration, Qualcomm can provide customers with better performance, lower power consumption, and more cost-effective connectivity solutions. In terms of organizational structure, Qualcomm has retained Atheros' core technology team and given them full autonomy to continue technological innovation. At the same time, Qualcomm has organically integrated Atheros engineers with its own R&D team, forming a complete technology chain covering from RF to applications. This deep integration strategy has achieved significant results. The Atheros technology team not only maintains its original innovative vitality, but also gains greater development space on the Qualcomm platform. And Qualcomm has greatly enhanced its strength in the field of connectivity technology through this integration. By acquiring Atheros, Qualcomm has successfully achieved a comprehensive layout in the field of wireless connectivity. Nowadays, Qualcomm is the only company in the world that can simultaneously operate in cellular Wi-Fi、 The company that provides top-level solutions among the three major wireless protocols of Bluetooth. This comprehensive technological capability provides solid support for Qualcomm's dominant position in the mobile communication market. In the smartphone market, almost all mainstream Android devices adopt Qualcomm's connectivity solutions. From the Samsung Galaxy series to Chinese brands such as Xiaomi, OPPO, Vivo, and from high-end flagships to mid to low end products, Qualcomm's connectivity technology is ubiquitous. The achievement of this market coverage is largely attributed to the contribution of Atheros technology. In the PC market, although Intel dominates in processors, Qualcomm also has strong competitiveness in Wi Fi connectivity. Many laptops using Intel processors have chosen Qualcomm's solutions for their Wi Fi modules. In the IoT and smart home markets, Qualcomm's connectivity technology has been widely applied. From smart speakers to smart home appliances, from industrial IoT to smart cities, Qualcomm's connectivity solutions provide reliable technical support for various application scenarios. One of the greatest values of Qualcomm's acquisition of Atheros is the unified optimization of multiple connectivity technologies. In modern mobile devices, cellular Wi-Fi、 Multiple connection technologies such as Bluetooth require collaborative work, while traditional separated designs often lead to issues such as increased power consumption, decreased performance, and poor user experience. By deeply integrating Atheros technology, Qualcomm has achieved unified design and optimization of multi connectivity technology. In the Snapdragon platform, various connectivity technologies share underlying resources such as RF front-end, antenna system, power management, etc., which not only reduces costs and power consumption, but also improves overall performance. If mobile chips are Qualcomm's signature, then connectivity technology is its invisible wing. By acquiring Atheros, Qualcomm not only gained world-class connectivity technology, but more importantly, completed its strategic transformation from a mobile chip manufacturer to a comprehensive communication solution provider. V2X and Vehicle Regulations Blueprint: Autotalks adds the finishing touch In the tide of intelligent driving, the "dialogue" between vehicles is moving from dreams to reality. The communication between vehicles (V2V) and between vehicles and infrastructure (V2I) together form the foundation of V2X (Vehicle to Everything) technology. These 'invisible dialogues' will become a key support for the safety and synergy of autonomous driving, and are a more' far sighted 'warning system than radar and cameras. Qualcomm has long regarded cars as the next highland of mobile Internet. From the Snapdragon Cockpit platform to the Snapdragon Ride positioning autonomous driving control platform, Qualcomm has built a multi-level automotive SoC system covering information entertainment, AI decision-making, sensor fusion, and more. However, what has been missing in this entire solution is the 'last mile' of V2X communication, a key technology. To this end, Qualcomm acquired the Israeli company Autotalks. This company has been deeply involved in the V2X chip field for many years and is one of the few chip manufacturers that can support both DSRC (Dedicated Short Range Communication) and C-V2X (Cellular Connected Vehicle Communication) dual protocols, with customers spread throughout the European and American automotive supply chains. Compared to the slow exploration of self-developed by major manufacturers, Autotalks' technology has been honed and matured through field testing and on-board processes, with the practical advantage of plug and play implementation. In 2023, this acquisition was quickly completed, and Qualcomm thus established a complete link from intelligent cockpit and autonomous driving control to the connection between the vehicle and the outside world. In the Snapdragon Ride platform, Qualcomm has integrated V2X modules natively for the first time, rather than providing them as external chips. This system level integration not only brings about power optimization and cost control, but more importantly, enhances the stability and synergy of V2X in the entire vehicle system, especially opening up new paths in the integration of AI and V2X information at the vehicle end. On a deeper level, this acquisition is not only a 'technological reinforcement', but also a bet on the future intelligent transportation landscape. Driven by 5G, the connection between cars and everything is no longer an isolated system, but an ecosystem of collaborative perception and decision-making. Whoever can occupy a pivotal position in this network holds the discourse power of "swarm intelligence" in autonomous driving. Autotalks is like a finishing touch to Qualcomm. It not only fills a technological gap, but also elevates Qualcomm's "vehicle specification blueprint" from single machine intelligence to collaborative intelligence - from in car intelligent systems to active cognition of the outside environment. This marks another crucial step for Qualcomm from being a "smart car chip supplier" to a "leader in intelligent transportation platforms". SerDes: The behind the scenes player in laying out high-speed interconnectivity If AI chips are powerful "factories" of computing power, then the data flowing between them is the "blood" that maintains the efficient operation of the entire system. What truly determines whether this blood can circulate efficiently is the often overlooked "data highway" - SerDes (serial parallel converter) technology. With the rapid development of AI reasoning, edge computing, automotive electronics and data center, data interconnection capability has become a new bottleneck of SoC system. The delay and bandwidth of data transmission, whether between internal modules of chips or between chips, often directly determine the performance limit of the entire platform. Qualcomm, which has always been known for its expertise in radio frequency and communication, realized early on that high-speed interconnection would be the key infrastructure that would determine the outcome in the process of advancing towards AI and data centers. But this is not Qualcomm's traditional strength. Faced with this "niche but crucial" technological gap, Qualcomm did not choose to develop from scratch, but instead took decisive action and quietly acquired some SerDes assets of Canadian technology company Alphawave Semi. Although not as well-known as some major manufacturers, Alphawave is a star company in the high-performance SerDes IP field, particularly skilled in high-speed interface solutions under various protocol standards such as PCIe, CXL, Ethernet, etc. Its technology enables high-speed transmission of data in a narrow physical channel with low power consumption and low bit error rate, which is crucial for cutting-edge SoC architectures such as processes below 5nm, Chiplet packaging, and multi Die interconnects. Through this acquisition, Qualcomm has quietly completed a "remedial lesson" in its high-speed I/O IP layout. Its strategic significance goes far beyond enhancing the data transmission capabilities of existing SoCs, but also focuses on the "underlying preparation" for Qualcomm's future entry into new battlefields such as data centers, AI acceleration cards, Chiplet heterogeneous computing platforms, etc. Especially in today's Chiplet trend, a single large chip is gradually being replaced by a combination of multiple small chips (Die), and the high-speed interconnection capability between chips has become a watershed for the success or failure of the platform. Without mature SerDes technology, Chiplets are like a puzzle that cannot be pieced together. With Alphawave's technological capabilities, Qualcomm can not only break through the internal "bottlenecks" of SoCs, but also build its own efficient modular platform architecture in the Chiplet era. More importantly, this interconnection capability is no longer limited to "internal optimization". It has become a bridge for Qualcomm to build the next generation of AI and communication fusion systems - whether it is the AI inference card on the server side or the collaborative work of different modules in the vehicle platform, SerDes technology is an irreplaceable "critical channel". In this competition over speed, latency, power consumption, and area, Qualcomm has quietly upgraded itself from a "chip company" to a "system interconnect layout provider" with a precise move. At the critical juncture of transitioning from the era of chips to the era of system integration, SerDes technology, this small screw, is supporting Qualcomm's next round of ambitions. At the end: What I bought is not only technology, but also the future The outside world often says that Qualcomm is a technology company, but in fact, it is more like the best example of capital and technology integration. Each of its core capabilities - graphics CPU、 Wireless communication, V2X, SerDes - almost all originated from strategic mergers and acquisitions. But what truly takes root and sprouts these abilities is Qualcomm's ability to internalize them into an ecosystem and unify them into a platform. It is not simply assembling parts, but melting them into an organic chip empire. This is a story that reached its peak through mergers and acquisitions, but it's not just about buying. It relies on digestion, integration, and re creation. From mobile phones to cars, from connectivity to computing, Qualcomm has made precise attacks time and time again, writing the legendary semiconductor empire that was "bought". As you can see, the foundation of the empire may have been bought, but tall buildings were built brick by brick.
    - June 15, 2025
  • 0.7nm chip, roadmap update
    0.7nm chip, roadmap update
    The main feature of GAA nanosheet devices is the vertical stacking of two or more nanosheet conductive channels, with each logic standard cell containing one stack for p-type devices and another stack for n-type devices. This configuration allows designers to further reduce the height of logical standard cells, defined as the number of metal lines (or tracks) per cell multiplied by the metal spacing. Designers can also choose to widen the channel at the expense of sacrificing unit height for larger driving current. In addition to the reduced area, GAA nanosheet transistors have another advantage over FinFETs: the gate surrounds the conductive channel from all directions, enhancing the gate's control over the channel even at shorter channel lengths. Figure 1- TEM image of GAA nanosheet device GAA nanosheet technology is expected to continue for at least three generations before chip manufacturers transition to CFET (complementary FET) technology. Due to its nMOS pMOS vertical stacking structure, the integration complexity of CFET is significantly higher than that of conventional nanosheet devices. According to IMEC's roadmap, the mass production of CFET is only feasible starting from node A7. This means that the era of GAA nanosheets must extend at least to the A10 technology node, where the unit height is expected to be as small as 90 nanometers. However, reducing the standard cell size based on GAA nanosheets without affecting performance is extremely challenging. This is exactly where forksheet device architecture may bring relief, as it is a non-destructive technology with greater scalability potential than conventional GAA nanosheet technology. Forksheet, 1nm reliance In 2017, IMEC launched the forksheet device architecture, first as a scaling booster for SRAM cells, and later as a scaling enabler for logic standard cells. The unique feature of its first implementation is the placement of a dielectric wall between nMOS and pMOS devices before gate patterning. Due to the fact that this wall is located in the middle of the logical standard unit, the architecture is referred to as an "inner wall" fork sheet. The wall physically isolates the p-gate trench from the n-gate trench, achieving a tighter n-to-p spacing than FinFET or nanosheet devices. This allows for further reduction of unit area (unit height up to 90nm) while still providing performance improvement. In this' inner wall 'configuration, these thin sheets are controlled by a tri gate forked structure, hence the name of the device. Figure 2- TEM image of the inner wall fork device At VLSI 2021, imec demonstrated the manufacturability of the 300mm inner wall fork sheet process flow. Conducting electrical characteristic tests on fully functional devices confirms that forksheet is the most promising device architecture, capable of extending the miniaturized roadmap of logic and SRAM nanosheets to the A10 node. Due to the reuse of most of the production steps of nanosheets in the integrated process, the technological evolution from nanosheets to forksheets can be considered non disruptive. Manufacturability is being challenged Despite the successful hardware demonstration, some concerns about manufacturability still exist, which has led IMEC to reconsider and improve its initial fork sheet device architecture. The main challenge is related to the manufacturability of the inner wall itself. In order to achieve a 90nm logic standard cell height, the dielectric wall needs to be very thin, within the range of 8-10nm. However, due to the early manufacturing of the equipment process, the wall will be exposed to all subsequent front-end process (FEOL) etching steps, which may further reduce the thickness of the wall, placing considerable demands on the selection of wall materials. In addition, in order to achieve process steps specific to n or p (such as p/n source/drain epitaxy), dedicated masks must be precisely placed on thin dielectric walls, which poses a challenge to the alignment of p/n masks. In addition, 90% of devices in practical applications have a common gate for n and p channels. In standard cells with inner wall forksheet devices, dielectric walls can hinder the pn connection gate. Unless the gate is made higher to cross the wall, which would increase parasitic capacitance. Finally, chip manufacturers are concerned about the three gate architecture, as the gate only surrounds the channel from three sides. Compared with the GAA structure, there is a risk of losing control over the channel at the gate, especially when the channel length is short. External wall fork: dielectric wall at the boundary of CELL At the Very Large Scale Integration Technology and Circuit Symposium 2025 (VLSI 2025), researchers from imec presented a novel fork sheet device architecture and named it the "outer wall fork sheet". They demonstrated through TCAD simulation how this outer wall forksheet improves its previous design by reducing process complexity, providing excellent performance, and maintaining area scalability. Figure 3- Imec's logical technology roadmap, showing the extension of the nanosheet era from 2nm to A10 node, using outer wall forksheet, and then transitioning to A7 and higher versions of CFET The outer wall forksheet places the dielectric wall at the boundary of the standard cell, making it a pp or nn wall. This allows each wall to be shared with adjacent standard cells and can be thickened (up to about 15 nanometers) without affecting the height of the 90 nanometer cells. Another significant feature is the wall cast integration method. The entire process begins with the formation of a wide Si/SiGe stack - a step that is repeated in any GAA technology. After etching away SiGe in the nanosheet channel release step, the stacked Si layer will form nanosheet shaped conductive channels. The dielectric wall will eventually divide the stack into two, with two FETs of similar polarity located on either side of the wall. The dielectric wall itself is processed towards the end of the integration process, that is, after the channel release of the nanosheets, source/drain etching, and source/drain epitaxial growth. The step of replacing the metal gate (RMG) has completed the integration process. Figure 4- Schematic diagram of the forksheet structure for the (top) inner wall and (bottom) outer wall 5 key improvements to the outer wall forksheet Compared with GAA nanosheet devices, inner and outer wall forksheets have two common advantages. In terms of area scaling, they are all able to achieve a 90nm logical standard cell height at the A10 node, which is more advantageous compared to the 115nm cell height in A14 nanosheet technology. The second common advantage is the reduction of parasitic capacitance: the two field-effect transistors (FETs) located on both sides of the wall (with n and p on the inner wall and n and n/or p and p on the outer wall) can be placed closer than units based on nanosheets without causing capacitance problems. In addition, the outer wall forks are expected to surpass the inner wall forks in five key aspects of design. Firstly, due to the adoption of the wall last integration method, the dielectric wall eliminates several complex FEOL steps. Therefore, it can be made from mainstream silica. In the back wall process step, walls are formed by forming trenches in a wide Si/SiGe stack and filling them with SiO2 dielectric. Secondly, as the wall is located at the boundary of the unit, its width can be relaxed to about 15nm, thereby simplifying the process. Thirdly, it is now easy to connect the gates of n and p devices within a standard cell without passing through dielectric walls. Fourthly, the outer wall forksheets are expected to provide better gate control than the inner wall devices, which is related to their ability to form Ω - gate structures instead of three gate forksheets. A wider dielectric wall makes it possible to etch the wall several nanometers in the final RMG step. This allows the gate to partially surround the fourth edge of the channel, forming a W-shaped gate and enhancing control over the channel. Through TCAD simulation, imec researchers found that etching off the 5-nanometer dielectric wall is the best choice, which can increase the driving current by about 25%. Figure 5- The effect of wall etching on gate formation: from triple gate to Ω gate, and then to GAA The fifth aspect is related to the potential of forksheet integrated flow to provide full channel strain, which is an additional performance improvement that is beneficial for driving current. Usually, full channel strain can be obtained by implementing source/drain stress sources. This method has been proven to be highly effective in (p-type) FinFETs, but it is difficult to implement in GAA nanosheets and inner wall forksheet device architectures. Conceptually, the idea is to incorporate Ge atoms into the source/drain regions. Due to the larger size of Ge atoms compared to Si atoms, they introduce compressive strain in the Si channel, thereby increasing the mobility of charge carriers. Figure 6- At the beginning of the outer wall fork sheet process, a "pre all" hard mask (brown) is deposited on top of a wide Si (gray)/SiGe (purple) layer stack. In this way, the Si "seed crystal" beneath the hard mask can support epitaxial growth of the source/drain electrodes The reason why the outer wall forksheet device can achieve fully effective source/drain stress sources is because it adopts the wall last method. Before making the wall, the hard mask will continue to cover the middle portion of the wide Si/SiGe stack, which will later be used to form the wall (Figure 6). The 'Si spine' beneath this hard mask can now serve as a seed crystal during source/drain epitaxial growth, acting as a silicon 'template' that extends from one gate channel to the next. This is similar to Si subfin in FinFET technology: imagine rotating the source/drain epitaxial module 90 ° (Figure 7). If there is no such silicon crystal template, vertical defects will form at the source/drain epitaxial interface, thereby eliminating the compressive strain formed in the silicon channel. Figure 7- The Si spine (right) in the outer wall fork sheet provides a continuous silicon crystal template from one gate channel to the next. This is conceptually similar to Si subfin in FinFET technology (left) External wall forksheet in SRAM and ring oscillator design Finally, IMEC conducted a benchmark study to quantify the power performance area (PPA) advantage of the outer wall fork sheet. When comparing the area of the A10 outer wall fork sheet and the SRAM bit cell based on A14 nanosheets, the area advantage of the nanosheet architecture becomes apparent. Layout display shows that the SRAM cell area based on the outer wall fork sheet has decreased by 22%, due to the reduction in the spacing between pp and nn on the basis of the reduction in gate spacing. Another key indicator for performance evaluation is the simulated frequency of the ring oscillator, expressed as the ratio of effective driving current to effective capacitance (I eff/C eff). Simulation shows that for node A10, an outer wall fork is required to maintain frequency consistency with the previous A14 and 2nm nodes, provided that all of these device structures can achieve full channel stress. It has been proven that achieving full channel stress in nanosheets (2nm and A14) and inner wall fork sheet devices is challenging, and its absence results in a drive current loss of approximately 33%. Therefore, it is expected that the ability to implement an effective source/drain stressor in the outer wall fork sheet device will result in further performance advantages in the design of ring oscillators. Figure 8- Simulation results of ring oscillator (with and without backend (BEOL) load) Outlook and Conclusion The fork blade device architecture was introduced by IMEC with the aim of extending the logic technology roadmap based on nanosheets to the A10 technology node and expecting CFET to achieve mass production. Due to manufacturability issues, IMEC abandoned the original inner wall fork design and developed an "upgraded" version: outer wall fork design. Compared to the inner wall fork sheet, the new design ensures higher manufacturability while improving performance and reducing surface area. Looking ahead to the future, IMEC is currently researching the compatibility between the outer wall forkfoot design and the CFET architecture, as well as to what extent CFET can benefit from PPA from this innovative expansion booster.
    - June 13, 2025
  • Semiconductor giant NXP plans to adjust its production line
    Semiconductor giant NXP plans to adjust its production line
    Recently, it was reported that Half NXP plans to close four 8-inch wafer fabs, one of which is located in Nijmegen, the Netherlands, and the other three are within the United States. As another key location of NXP in the Netherlands besides its headquarters in Eindhoven, Nijmegen's business includes manufacturing, research and development, testing, technology enablement, and support functions, playing an important role in the process of introducing new products. Behind this, NXP plans to transition production to a new 12 inch wafer fab: even without considering edge loss, the production of 12 inch monocrystalline wafers is 2.25 times that of 8-inch wafers, which means lower fixed and manufacturing costs and higher profits. Therefore, NXP plans to close the four wafer fabs mentioned above in the next 10 years. In addition, the 12 inch wafer fab built by NXP and the world's leading joint venture VSMC in Singapore will begin mass production in 2027, which will help reduce the risk of NXP's capacity building. This factory focuses on the production of mixed signal, power management, and analog chips from 130nm to 40nm. It is expected to achieve a monthly production scale of 55000 wafers by 2029, becoming an important manufacturing hub for NXP in the Asia Pacific region. NXP's strategic adjustment is not an isolated case, but a microcosm of the global semiconductor industry upgrading. With the explosive growth of demand for AI and data centers, it has driven the market towards more efficient and lower cost manufacturing technologies. According to SEMI's statistics, it is expected that 82 new 12 inch chip facilities and production lines will be built globally between 2023 and 2026. By 2026, the production capacity of 12 inch wafer fabs will increase to 9.6 million wafers per month. According to relevant data, 12 inch wafers account for about 65% of the total semiconductor wafer shipments, while 8-inch wafers account for about 20%, with the remaining portion mainly consisting of smaller sized wafers. Dr. Li Wei, Executive Vice President of Shanghai Silicon Industry, believes that 2024 may be a turning point for the exit of 8-inch silicon wafers from the historical stage. Because the integrated circuit industry tends to eliminate outdated production capacity technologies during industrial adjustments. Industry analysis suggests that NXP's 12 inch transformation is the result of a combination of technological iteration, market demand, and industry competition. Despite facing challenges such as equipment costs and process complexity, it is gradually building a composite production capacity system that covers advanced and mature processes through joint ventures, contract manufacturing, and other models. However, it needs to find a new balance between technological breakthroughs, cost control, and regional layout.
    - June 11, 2025
  • 17.2 billion yuan! The semiconductor giant just announced
    17.2 billion yuan! The semiconductor giant just announced
    Qualcomm agreed to acquire British semiconductor company Alphawave IP Group on Monday. Qualcomm said the enterprise value of the transaction is approximately US$2.4 billion (approximately RMB 17.2 billion). Under the terms of the acquisition, each AlphaWave shareholder will be entitled to receive $2.48 in cash for each share of AlphaWave stock. AlphaWave said the board of directors unanimously recommended that AlphaWave shareholders vote in favor of the plan. It is reported that after two months of negotiations, Alphawave agreed to accept Qualcomm's $2.4 billion acquisition offer. The price is equivalent to 183 pence per share (approximately RMB 16.07), a 96% premium over the company's closing price of 93.50 pence (approximately RMB 9.09) on March 31 (the day before Qualcomm announced its acquisition intention). Alphawave focuses on developing high-speed semiconductors and connection technologies for data centers and artificial intelligence applications. Alphawave designs and licenses semiconductor technology for data centers, networks, and storage. Its "serializer/deserializer" (SerDes) technology attracted acquisition interest from Qualcomm and SoftBank's chip technology provider Arm in early April. But according to previous reports in April, Arm withdrew after preliminary discussions with Alphawave. SerDes technology is an indispensable part of artificial intelligence applications. Chatbots like ChatGPT usually require thousands of chips to work together to ensure smooth operation. As one of Broadcom's core competitive advantages, SerDes is a key factor in winning AI customers such as Google and OpenAI.
    - June 09, 2025
  • TI plans to increase prices for some product lines
    TI plans to increase prices for some product lines
    TI plans to increase prices for some product lines, effective from June 15th. The average price increase this time is over 10%, with some part numbers experiencing a price increase of 40-70% or more. The price increase materials are mainly concentrated in three types of products: low profit margins, old part numbers, and promised quantities that have not been met. This is a global price increase, not only for the China region. The price increase in the China region is mainly for low profit margin products, involving part numbers such as operational amplifiers and interface ADCs.
    - June 06, 2025
  • Chipanalog CA-PM4644BA four-channel fully integrated multi-phase DCDC micromodule
    Chipanalog CA-PM4644BA four-channel fully integrated multi-phase DCDC micromodule
    In the era of high-density integration of digital circuits, the efficiency, flexibility and reliability of power supply systems have become core challenges. Chipanalog has launched a new CA-PM4644BA wide voltage input four-channel DC/DC buck converter module, which provides high-precision power supply solutions for FPGA, communication storage and other scenarios with three advantages: multiple outputs, flexible expansion and ultra-high integration. 01 Product Overview   CA-PM4644BA is a step-down DC/DC converter with wide input voltage and 4A output for all four channels. The four channels can also be used in parallel to provide a maximum output current of 16A. The device adopts BGA77 package, and integrates switch control circuit, power MOSFET, power inductor, decoupling capacitor and other circuit components. Therefore, only a few external components are required, such as input capacitor, output capacitor, feedback resistor, etc., to form a complete step-down four-way DC/DC regulator. The input voltage range of CA-PM4644BA is 4V~15V, and the output voltage can be set in the range of 0.6V~5.5V by changing the feedback external resistor. CA-PM4644BA application circuit is often used as a load power supply, which can provide high-precision voltages of different specifications such as 1.0V, 1.2V, 1.5V, 1.8V, 3.3V, 5V, etc. for digital circuits in the whole system, such as FPGA control circuits, motherboards and CPUs, communication storage and other circuits, and provide a maximum output current of 4A. CA-PM4644BA can also flexibly configure 4 channels for parallel use, continuously providing output currents of up to 8A (two-phase parallel) and 16A (four-phase parallel).   02 Features   Multiple outputs, flexible expansion: one "core" meets the needs of multiple scenarios Four-channel independent power supply: single-channel 4A output capacity, four channels can independently power different loads (such as 1.8V/3.3V/5V multi-voltage requirements). Parallel output up to 16A: Four channels can be flexibly connected in parallel, supporting 8A (two-phase) and 16A (four-phase) high current output, suitable for high-power core power supply such as CPU/GPU. Wide voltage coverage: input 4V-15V, output 0.6V-5.5V adjustable, accurately matching the power supply requirements of digital circuits. Highly integrated design: Simplify the system and save space. BGA77 package (9mm×15mm×5.01mm), internally integrated switching circuits, MOSFET, inductors, capacitors and other core components, only a small amount of resistors and capacitors are required on the periphery to work. Reduce PCB area occupation and help high-density circuit design. Efficient and stable: A reliable choice in harsh environments. Efficiency is as high as 95% (5V input, 3.3V/1A output), reducing system power consumption and temperature rise. ±1.5% output voltage accuracy, combined with COT control mode, to achieve fast dynamic response and low ripple. -40℃~125℃ wide temperature operation, supporting industrial and automotive environment applications. Multiple protections: Built-in input overvoltage protection, output overcurrent/overvoltage protection, support soft start and temperature monitoring functions to protect the system from damage to the equipment under abnormal conditions.   03 Typical application scenarios FPGA/ASIC power supply: provides 1.0V/1.2V low voltage, high-precision power supply for multi-core processors and logic units. Communication base station and server: Supports multi-channel power management for 5G base station BBU and data center storage modules.
    - June 04, 2025
  • Chip giant, heading to India
    Chip giant, heading to India
      In recent years, in the current context of the global semiconductor industry's anti globalization wave and geopolitical games, India is rising at an impressive speed as the core coordinate of the strategic layout of international chip giants. From Renesas Electronics announcing the launch of 3nm advanced process research and development in India, to Texas Instruments settling its smallest MCU design team in Bangalore, to Foxconn partnering with HCL to build a semiconductor packaging base A 'India fever' is unfolding across the entire industry chain of chip design, manufacturing, and packaging. Indian semiconductor, lively now Renesas 3nm, strong entry into India On May 13, 2025, Japanese semiconductor giant Renesas Electronics launched two 3nm chip design centers in Noida and Bangalore, India. This is India's first 3nm chip design project and marks a crucial step in its semiconductor ambitions. Renesas 3nm Design Center focuses on the research and development of automotive grade and high-performance computing chips, with plans for mass production in the second half of 2027. The project has received strong support from the Indian government, with over 270 academic institutions receiving EDA software and learning kits for engineer training. Renesas plans to increase its workforce in India to 1000 by the end of 2025 and collaborate with over 250 academic institutions and startups through its "Semiconductor Program" and "Production Linked Incentive Program (PLI)". In the manufacturing process, Renesas, together with India's CG Power and Thailand's Star Microelectronics, has invested 76 billion rupees (approximately 920 million US dollars) in Gujarat to build an outsourcing packaging and testing plant, focusing on defense and space chip packaging. It collaborates with Tata Group's 28nm wafer fab to build a "design manufacture package" full industry chain. Renesas focuses on end-to-end capability expansion and hopes to obtain a 50% financial subsidy through cooperation with the Indian government, while deeply integrating into the Indian talent development system. India plans to train 85000 VLSI engineers and support 100 startups within five years, with the goal of building India into Renesas' second-largest global research and development base.   The Indian Ministry of Electronics and Information Technology sees it as a 'major leap' in the semiconductor roadmap, aiming to achieve a semiconductor output value of $109 billion by 2030, accounting for 10% of the global market. However, the project implementation faces many challenges. In the manufacturing process, the precision requirements for 3nm process equipment are extremely high, and only a few companies such as TSMC and Samsung can mass produce it globally. Renesas plans to outsource to TSMC for outsourcing, but geopolitical risks may affect the stability of outsourcing. On the supply chain, India's domestic system is not perfect, and the supply of raw materials and equipment relies on imports, resulting in high and unstable costs. On the technical level, although India has a large group of engineers, they lack high-end design experience and currently only have mature process design capabilities. The 3nm process has extremely high requirements for transistor density and energy efficiency optimization, and there is a lack of IP libraries and design toolchains locally, requiring external support. The ambition and challenges of India's semiconductor industry coexist, and the landing of Renesas' 3nm design center is an important progress. However, whether it can overcome manufacturing dependence, supply chain difficulties, and technological shortcomings in the future will determine whether it can truly occupy a place in the global semiconductor landscape. Foxconn and HCL Joint Venture: Building Semiconductor Packaging Plant in India On May 14, 2025, the Indian Cabinet approved the joint venture between Foxconn and HCL Group to build a semiconductor packaging plant, with a total investment of 37.06 billion rupees (approximately 435 million US dollars), located at Jawar Airport in Uttar Pradesh, and expected to start production in 2027. The project is divided into two phases, with the first phase focusing on packaging testing and the second phase upgrading to a complete manufacturing factory, ultimately achieving a monthly production capacity of 20000 wafers and 36 million display driver chips. In terms of technology and product planning, in the initial stage of the project, we will provide downstream services for overseas chips to avoid the shortcomings of domestic manufacturing in India; The second phase will shift towards the manufacturing of display driver chips, covering fields such as mobile phones and automobiles, forming a vertically integrated ecosystem of "chip module whole machine" with Foxconn's iPhone assembly plant in India. The project is deeply tied to Apple's supply chain restructuring needs. Currently, Indian made iPhones account for 20% of US imports, and Apple plans to expand production capacity in India to cope with geopolitical risks. Foxconn not only responds to Apple's "Made in India" strategy, but also reduces import tariffs on electronic components by 20% through localized chip supply. Its panel factory, which cooperates with Innolux Optoelectronics, will also collaborate with packaging factories to promote localization of the display industry chain. This project is the sixth semiconductor manufacturing project approved by India, supported by the "Semiconductor Plan" policy. The Indian government provides capital subsidies, land concessions, and tax exemptions, and Uttar Pradesh also grants exemptions from electricity taxes and grants for skills training. Foxconn holds 40% of the shares and HCL Group holds 60%. Both parties plan to adopt a "technology introduction+local operation" model to build automotive electronic manufacturing capabilities, and plan to build two more wafer fabs and one packaging plant in the future. As of May 2025, the project has completed company registration and site survey, and is expected to start infrastructure construction by the end of the year.   HCL Group is in talks with NXP and Tesla to establish OEM cooperation for automotive display driver chips. However, the project faces multiple challenges. India lacks sufficient accumulation of display driver chip technology, and although Foxconn has introduced panel technology, chip design relies on external IP authorization.   In addition, the global market is dominated by Samsung and LG, and Foxconn needs to break through technical indicators to enter the mainstream supply chain. Moreover, India can only absorb 30% of its domestic production capacity, and the remaining capacity depends on exports. Geopolitical risks may affect order stability. Overall, this cooperation is an important attempt for India's semiconductor "differentiation breakthrough". If mass production goes smoothly, it is expected to form regional advantages. However, to achieve a leap from "packaging and testing" to "independent design and manufacturing", many bottlenecks such as technology and production capacity still need to be overcome. TSMC to build its first 12 inch wafer fab in India In September 2024, TSMC signed a contract with India's Tata Electronics to jointly build India's first 12 inch wafer fab in Gujarat, with a total investment of $11 billion and a monthly production capacity of 50000 wafers. It is expected to start mass production in 2026. This project is not only a milestone in semiconductor manufacturing in India, but also a key part of TSMC's global layout. TSMC is responsible for the design and construction of wafer fabs, transfer of mature process technology (28nm and above processes), and talent training, while Tata Group undertakes over 90% of investment and operational management. Both parties will build a full industry chain ecosystem of "design manufacturing packaging" through a "technology authorization+local operation" model. The factory focuses on automotive grade, panel drivers, and high-speed computing logic chips, with target markets covering electric vehicles, AI, and other fields. Tata Electronics has negotiated OEM cooperation with NXP and Tesla, and plans to build two more factories in the future to simultaneously promote the construction of the Assam packaging plant. For TSMC, technology transfer can consolidate its mature process influence and obtain market access at low cost through India's "Semiconductor Plan" subsidy of 760 billion rupees and the "Production Linked Incentive Plan". The Indian government provides up to 50% financial subsidies for the project, promising land concessions and tax reductions. India has included the project in its "Self Reliance India" strategy, aiming to cultivate 50000 semiconductor talents and increase self-sufficiency to 50% by 2030. At present, 30% of the factory infrastructure has been completed, 12 mature process patents have been transferred, the first batch of 500 students have entered the training stage, and Tata and NXP's OEM cooperation has entered the technology verification stage. However, the project faces numerous challenges.   In terms of the market, there is overcapacity in mature processes worldwide, and the demand in India may be difficult to digest the scale of producing 50000 pieces per month, requiring reliance on OEM orders to balance production capacity. In terms of policy implementation, India's previous $10 billion subsidy plan had little effect due to slow approval and low participation, and it is doubtful whether this subsidy can be delivered on time. The cooperation between TSMC and Tata is a bold attempt by India's semiconductor industry to achieve "leapfrog development". Its success or failure depends not only on technology transfer, but also on the Indian government's sustained efforts in policy implementation, infrastructure support, and market cultivation. Infineon opens research and development center in India On March 24, 2025, Infineon officially opened its Global Competence Center (GCC) in Ahmedabad, Gujarat, India. As its fifth research and development base in India, the center is located in GIFT City and plans to hire 500 engineers over the next five years, focusing on chip design, product software development, information technology, supply chain management, and system application engineering. Currently, Infineon has over 2500 employees in India, with Bangalore being its largest research and development base. Infineon regards India as a global innovation core, aiming to achieve sales of over 1 billion euros by 2030, closely focusing on India's automotive regulations and industrial chip demand, and accelerating its layout with up to 50% financial subsidies under the "Semiconductor Plan". It adopts a "localization of research and development+outsourcing of manufacturing" model, with a focus on developing next-generation automotive specifications and industrial control chips on the R&D side, and utilizing Indian engineers to reduce costs; The manufacturing side has reached a wafer supply agreement with Indian companies CDIL and Kaynes, with Indian companies responsible for packaging, testing, and sales, forming a "design packaging sales" collaborative chain. Currently, there are no plans to build a self built wafer fab, and the strategy may be adjusted in the long term based on the maturity of the Indian supply chain. In addition, Infineon actively builds a local ecosystem, collaborates with universities to cultivate semiconductor talents, and deepens government enterprise cooperation by leveraging preferential policies such as land and taxation in Gujarat. It aims to capture over 10% of the $100 billion semiconductor market in India by 2032. Infineon's India layout is a key outcome of its "global localization" strategy, attempting to seize the opportunity during India's semiconductor boom period and help India transform into a "manufacturing powerhouse" through research and development centers, local cooperation networks, and policy resource integration. Micron is building a sealing and testing factory in India   The factory focuses on wafer segmentation, packaging, testing, and module production. It is expected that the first batch of products will be produced in the first half of 2025, and after full production, it will create over 5000 high-tech jobs and become a large-scale storage chip packaging and testing base in South Asia. The site selection forms a 50 kilometer industrial cluster with Tata Electronics wafer fab and Renesas Electronics packaging and testing project, and initially constructs a closed loop of "design manufacturing packaging and testing" area. The factory adopts mature processes of 40nm and above to serve the Indian, Southeast Asian, and Middle Eastern markets, which can reduce Micron Asia Pacific's packaging and testing costs by 15% -20%. In the progress of the project, Micron is promoting the localization of the supply chain, Korean material suppliers are investing with factories, Indian local enterprises are also cooperating in equipment maintenance, chemical supply and other fields, and the US government is providing key raw material support. Although production has been delayed by 6 months due to India's infrastructure shortcomings, Micron still sees great potential in the Indian market. This project is a result of the Modi government's "Self Reliance India" strategy, marking a breakthrough in India's chip manufacturing process. As India plans to launch a new round of semiconductor incentive policies worth over billions of dollars, Micron is evaluating phase two expansion and plans to increase monthly testing capacity to 150000 wafers by 2030, covering advanced technologies. Micron's layout in India demonstrates India's determination and potential to accelerate its transformation into a new global hub for chip manufacturing through "policy leverage+international cooperation". Semiconductor giants gather in India In addition, many leading global semiconductor companies are accelerating the construction of strategic pivot points in India. Chip giants such as NVIDIA and AMD have taken the lead in establishing large-scale research and design centers in India, integrating India into their global innovation network to diversify supply chain risks and stay close to the rapidly growing consumer electronics market. As a leader in the automotive chip industry, NXP announced that it will double its R&D investment in India to over $1 billion in the coming years. Currently, it has four design centers and 3000 employees, and plans to establish a second R&D department focused on 5-nanometer automotive chips at the Greater Noida Semiconductor Park, with the goal of increasing the total number of employees to 6000. Qualcomm, TI and other companies have established research and development centers and localized teams to deeply participate in the technological development of emerging fields such as 5G communication and the Internet of Things in India. ADI has formed a strategic alliance with Tata Group to explore the construction of semiconductor manufacturing plants in India, with a focus on developing customized chips for electric vehicles and network infrastructure. This move marks the beginning of international manufacturers extending from the design phase to the manufacturing phase. These layouts resonate with the industrial policies of the Indian government. India has attracted $10 billion wafer fab projects, including a collaboration between Israel's Tower Semiconductor and Adani Group, by revising its $10 billion semiconductor incentive plan, relaxing technology requirements, and increasing subsidy ratios. In addition, global semiconductor equipment giants are also accelerating the construction of strategic pivot points in India, deeply participating in the reshaping of its industrial ecosystem, and improving the layout of the industrial chain. DISCO Japan was the first to establish a legal entity in Bangalore and a service network in Ahmedabad. The initial team of 10 people will be expanded according to customer needs. Its layout aims to provide equipment installation and technical support for Micron, Tata Electronics, and other wafer fabs and packaging and testing plants in India. It also trains Indian marketing personnel in advance through its Singapore base. Applied Materials positions India as a global hub for research and supply chain, and the $400 million investment plan launched in 2023 is steadily advancing. Establishing a Center of Excellence for Artificial Intelligence and Data Science in Chennai, focusing on the development of AI applications for chip manufacturing, with an expected creation of 500 high-end positions. The plan is to expand the total number of employees from 8000 to 10000. At the same time, we are collaborating with 15 suppliers to explore the establishment of equipment component manufacturing bases in India, striving to physically co locate verification centers with wafer fabs, shorten research and development cycles, improve material verification efficiency, and help India form competitiveness in mature process areas. Lam Research (Panlin Group) is implementing a "localization of supply chain" strategy and announced a $1.2 billion investment in Karnataka state in 2024 to collaborate with the local government to promote the construction of local supply capabilities such as precision components and high-purity gas delivery systems. The company evaluates the potential for cooperation between Indian suppliers in the core components of wafer manufacturing equipment and plans to include India in a global network of 3000 suppliers to achieve localized support in key equipment areas such as etching and thin film deposition, thereby enhancing regional supply chain resilience and reducing supply chain risks in the Asia Pacific region. Tokyo Electronics has established a deep cooperation with India's Tata Electronics to supply equipment for its 12 inch wafer fab in Gujarat, and will also establish a specialized training system to help Tata Electronics engineers master advanced process equipment operation techniques. We plan to establish an equipment delivery and after-sales support system in India by 2026, and form a local engineering team to serve Tata Electronics' manufacturing needs in areas such as automotive electronics and AI chips. The layout of giants resonates with India's industrial policies, with central and local governments providing up to 75% of project cost subsidies to promote the coordinated development of equipment giants and wafer fabs. The influx of international capital confirms the strategic value of the Indian market. Its appeal lies not only in the expected chip demand to exceed 100 billion US dollars by 2026, making it the fastest-growing semiconductor market in the world, but also in the explosive growth in fields such as automotive electronics and 5G communication, providing broad application scenarios for the semiconductor industry. Although the Indian semiconductor industry is still constrained by weak infrastructure and insufficient technological accumulation, it is gradually moving from a major chip design outsourcing country to the manufacturing sector through "policy leverage+international cooperation". With the deep participation of leading semiconductor companies, India is expected to form differentiated competitiveness in sub sectors such as automotive electronics and industrial control, becoming an important variable in the restructuring of the global semiconductor supply chain.   The Story of India's Semiconductor Industry In fact, the development process of India's semiconductor industry is full of twists and turns and opportunities, from early technological breakthroughs to policy adjustments, and now global giants are laying out, reflecting a country's unremitting exploration in the semiconductor field. The starting point of India's semiconductor industry can be traced back to 1984, when the government funded semiconductor manufacturing company SCL upgraded its process from 5 microns to 0.8 microns in the 1980s, only one generation behind Intel. However, a major fire in 1989 destroyed the SCL factory, and reconstruction took 8 years, causing India to miss the golden period of semiconductor development. Since then, India has made multiple attempts to attract foreign investment to build factories, but has repeatedly suffered setbacks due to lagging policies and insufficient resources. For example, in 2005, Intel gave up investment due to policy deficiencies, and in 2012, incentive plans were stalled due to capital and water resource issues. Until December 2021, the Modi government launched the "India Semiconductor Plan", providing 760 billion rupees (approximately 10 billion US dollars) in incentive funds, but the initial response was limited. The real turning point came in June 2023, when the revised plan increased the financial support ratio to 50%, covering the entire industry chain of semiconductor manufacturing, packaging and testing, and relaxed technical requirements to attract giants such as Micron and Renesas to settle in. This policy adjustment marks India's shift from slogan based incentives to substantive industrial support. Under policy promotion, the Indian semiconductor industry has made significant progress. In addition to the manufacturers mentioned above, almost all of the world's top semiconductor companies, including Intel, Texas Instruments, Nvidia, Qualcomm, etc., have design and research centers in India, with most personnel concentrated in Bangalore, Karnataka state in southern India. Image source: ISM In addition, India has signed multiple cooperation agreements with the United States, Japan, and the European Union to promote technology transfer and supply chain diversification. Market data shows that semiconductor consumption in India is expected to grow from $22 billion in 2019 to $64 billion in 2026, with a compound annual growth rate of 16%, with automotive, consumer electronics, and wireless communications being the main growth areas.   Reasons for Semiconductor Giants to Invest in India There are several reasons why international semiconductor giants are rushing to India, in my opinion: Policy and financial support: India provides the most generous subsidy policy in the world, with the central government bearing 50% of project costs and state governments providing additional subsidies of 20% -25%. Enterprises only need to contribute 25% -30% in actual investment, directly lowering the investment threshold for enterprises. The revised plan also provides special support for sub sectors such as packaging and testing, compound semiconductors, etc., to further reduce investment risks for enterprises. Image source: India Semiconductor Mission (ISM) Talent reserve and cost advantage: India has 20% of the world's semiconductor design talent, 25 leading companies such as Intel and Qualcomm have established research and development centers in Bangalore, and companies such as New Think Technology have over 5500 employees. Every year, 100000 new engineering graduates are added, providing sufficient manpower reserves for the industry, and the labor cost is only one-third of that in developed countries. Intel, Qualcomm and other companies have established research and development centers in India, utilizing local talents for chip design and software development; Equipment giants such as Applied Materials and Lam Research are expected to train tens of thousands of engineers in the next five years through training programs. Geopolitics and Supply Chain Restructuring: Under the trend of China US trade frictions and global supply chain diversification, India has become an important choice for companies to diversify their risks. Semiconductor giants can avoid geopolitical risks and stay close to rapidly growing local markets such as automotive electronics and 5G equipment by setting up factories in India. The Memorandum of Understanding on Semiconductor Supply Chain and Innovation Partnership signed between India and the United States further strengthens its position as a "reliable manufacturing center". Market potential and industry synergy: The size of the Indian semiconductor market is expected to reach $110 billion by 2030, and the government is promoting the "Make in India" and "Digital India" plans to stimulate local demand. At the same time, India is building a complete industrial chain through local giants and international cooperation, constructing a complete ecosystem from design, manufacturing to packaging, attracting upstream and downstream enterprises to gather, forming industrial clusters, and reducing collaboration costs between enterprises. Meanwhile, Apple's production of iPhones in India can also drive demand for chip matching. Infrastructure upgrade: India is building a "semiconductor city" in Gujarat, with supporting infrastructure such as electricity and transportation, and establishing a semiconductor manufacturing ecosystem fund for park development and logistics network construction. In addition, the Indian government is promoting the "Digital India" plan, investing 11000 kilometers of highways and smart grids to improve supply chain efficiency.
    - June 02, 2025
  • The United States demands that the three major EDA giants completely cut off their supply to China
    The United States demands that the three major EDA giants completely cut off their supply to China
    According to the Financial Times, the Bureau of Industry and Security (BIS) of the US Department of Commerce has reportedly issued notices to the top three global electronic design automation (EDA) software suppliers - Synopsys, Cadence, and Siemens EDA - requesting them to cease providing services to Chinese customers. Another industry insider confirmed that these three companies did receive notification from BIS, but the specific content is still unclear.   Insiders have revealed that the US government is evaluating a broader policy to restrict the sale of chip design software to China. As part of the action, BIS has recently sent letters to some leading EDA suppliers requesting a suspension of shipments to Chinese customers. In response, a BIS spokesperson stated, "The US Department of Commerce is reviewing exports involving strategic projects in China. In some cases, existing export licenses may be suspended or additional license requirements may be imposed during the review period Sassine Ghazi, CEO of New Think Technology, stated in a conference call on May 28th that the company has not yet received formal notification from BIS, but he acknowledged reports of the letter, stating, "We cannot speculate on the potential impact of the notification that has not yet been received.   The United States' implementation of EDA supply cut-off to China is not the first time. In 2019, after Huawei was included in the "Entity List", New Think Technology, Kaiden Electronics, and Mentor Graphics (now Siemens EDA) were required to suspend software licensing and updates to Huawei.   In August 2022, the US Department of Commerce further tightened export controls on EDA tools used for advanced process chip design at 3 nanometers and below, aimed at limiting China's development in the field of cutting-edge chip design. These ongoing measures indicate that cutting off EDA supply to China is a key link in the US semiconductor strategy, with the core goal of curbing China's ability to improve in high-end chip design and manufacturing.  
    - May 30, 2025
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