The main feature of GAA nanosheet devices is the vertical stacking of two or more nanosheet conductive channels, with each logic standard cell containing one stack for p-type devices and another stack for n-type devices. This configuration allows designers to further reduce the height of logical standard cells, defined as the number of metal lines (or tracks) per cell multiplied by the metal spacing. Designers can also choose to widen the channel at the expense of sacrificing unit height for larger driving current. In addition to the reduced area, GAA nanosheet transistors have another advantage over FinFETs: the gate surrounds the conductive channel from all directions, enhancing the gate's control over the channel even at shorter channel lengths. Figure 1- TEM image of GAA nanosheet device GAA nanosheet technology is expected to continue for at least three generations before chip manufacturers transition to CFET (complementary FET) technology. Due to its nMOS pMOS vertical stacking structure, the integration complexity of CFET is significantly higher than that of conventional nanosheet devices. According to IMEC's roadmap, the mass production of CFET is only feasible starting from node A7. This means that the era of GAA nanosheets must extend at least to the A10 technology node, where the unit height is expected to be as small as 90 nanometers. However, reducing the standard cell size based on GAA nanosheets without affecting performance is extremely challenging. This is exactly where forksheet device architecture may bring relief, as it is a non-destructive technology with greater scalability potential than conventional GAA nanosheet technology. Forksheet, 1nm reliance In 2017, IMEC launched the forksheet device architecture, first as a scaling booster for SRAM cells, and later as a scaling enabler for logic standard cells. The unique feature of its first implementation is the placement of a dielectric wall between nMOS and pMOS devices before gate patterning. Due to the fact that this wall is located in the middle of the logical standard unit, the architecture is referred to as an "inner wall" fork sheet. The wall physically isolates the p-gate trench from the n-gate trench, achieving a tighter n-to-p spacing than FinFET or nanosheet devices. This allows for further reduction of unit area (unit height up to 90nm) while still providing performance improvement. In this' inner wall 'configuration, these thin sheets are controlled by a tri gate forked structure, hence the name of the device. Figure 2- TEM image of the inner wall fork device At VLSI 2021, imec demonstrated the manufacturability of the 300mm inner wall fork sheet process flow. Conducting electrical characteristic tests on fully functional devices confirms that forksheet is the most promising device architecture, capable of extending the miniaturized roadmap of logic and SRAM nanosheets to the A10 node. Due to the reuse of most of the production steps of nanosheets in the integrated process, the technological evolution from nanosheets to forksheets can be considered non disruptive. Manufacturability is being challenged Despite the successful hardware demonstration, some concerns about manufacturability still exist, which has led IMEC to reconsider and improve its initial fork sheet device architecture. The main challenge is related to the manufacturability of the inner wall itself. In order to achieve a 90nm logic standard cell height, the dielectric wall needs to be very thin, within the range of 8-10nm. However, due to the early manufacturing of the equipment process, the wall will be exposed to all subsequent front-end process (FEOL) etching steps, which may further reduce the thickness of the wall, placing considerable demands on the selection of wall materials. In addition, in order to achieve process steps specific to n or p (such as p/n source/drain epitaxy), dedicated masks must be precisely placed on thin dielectric walls, which poses a challenge to the alignment of p/n masks. In addition, 90% of devices in practical applications have a common gate for n and p channels. In standard cells with inner wall forksheet devices, dielectric walls can hinder the pn connection gate. Unless the gate is made higher to cross the wall, which would increase parasitic capacitance. Finally, chip manufacturers are concerned about the three gate architecture, as the gate only surrounds the channel from three sides. Compared with the GAA structure, there is a risk of losing control over the channel at the gate, especially when the channel length is short. External wall fork: dielectric wall at the boundary of CELL At the Very Large Scale Integration Technology and Circuit Symposium 2025 (VLSI 2025), researchers from imec presented a novel fork sheet device architecture and named it the "outer wall fork sheet". They demonstrated through TCAD simulation how this outer wall forksheet improves its previous design by reducing process complexity, providing excellent performance, and maintaining area scalability. Figure 3- Imec's logical technology roadmap, showing the extension of the nanosheet era from 2nm to A10 node, using outer wall forksheet, and then transitioning to A7 and higher versions of CFET The outer wall forksheet places the dielectric wall at the boundary of the standard cell, making it a pp or nn wall. This allows each wall to be shared with adjacent standard cells and can be thickened (up to about 15 nanometers) without affecting the height of the 90 nanometer cells. Another significant feature is the wall cast integration method. The entire process begins with the formation of a wide Si/SiGe stack - a step that is repeated in any GAA technology. After etching away SiGe in the nanosheet channel release step, the stacked Si layer will form nanosheet shaped conductive channels. The dielectric wall will eventually divide the stack into two, with two FETs of similar polarity located on either side of the wall. The dielectric wall itself is processed towards the end of the integration process, that is, after the channel release of the nanosheets, source/drain etching, and source/drain epitaxial growth. The step of replacing the metal gate (RMG) has completed the integration process. Figure 4- Schematic diagram of the forksheet structure for the (top) inner wall and (bottom) outer wall 5 key improvements to the outer wall forksheet Compared with GAA nanosheet devices, inner and outer wall forksheets have two common advantages. In terms of area scaling, they are all able to achieve a 90nm logical standard cell height at the A10 node, which is more advantageous compared to the 115nm cell height in A14 nanosheet technology. The second common advantage is the reduction of parasitic capacitance: the two field-effect transistors (FETs) located on both sides of the wall (with n and p on the inner wall and n and n/or p and p on the outer wall) can be placed closer than units based on nanosheets without causing capacitance problems. In addition, the outer wall forks are expected to surpass the inner wall forks in five key aspects of design. Firstly, due to the adoption of the wall last integration method, the dielectric wall eliminates several complex FEOL steps. Therefore, it can be made from mainstream silica. In the back wall process step, walls are formed by forming trenches in a wide Si/SiGe stack and filling them with SiO2 dielectric. Secondly, as the wall is located at the boundary of the unit, its width can be relaxed to about 15nm, thereby simplifying the process. Thirdly, it is now easy to connect the gates of n and p devices within a standard cell without passing through dielectric walls. Fourthly, the outer wall forksheets are expected to provide better gate control than the inner wall devices, which is related to their ability to form Ω - gate structures instead of three gate forksheets. A wider dielectric wall makes it possible to etch the wall several nanometers in the final RMG step. This allows the gate to partially surround the fourth edge of the channel, forming a W-shaped gate and enhancing control over the channel. Through TCAD simulation, imec researchers found that etching off the 5-nanometer dielectric wall is the best choice, which can increase the driving current by about 25%. Figure 5- The effect of wall etching on gate formation: from triple gate to Ω gate, and then to GAA The fifth aspect is related to the potential of forksheet integrated flow to provide full channel strain, which is an additional performance improvement that is beneficial for driving current. Usually, full channel strain can be obtained by implementing source/drain stress sources. This method has been proven to be highly effective in (p-type) FinFETs, but it is difficult to implement in GAA nanosheets and inner wall forksheet device architectures. Conceptually, the idea is to incorporate Ge atoms into the source/drain regions. Due to the larger size of Ge atoms compared to Si atoms, they introduce compressive strain in the Si channel, thereby increasing the mobility of charge carriers. Figure 6- At the beginning of the outer wall fork sheet process, a "pre all" hard mask (brown) is deposited on top of a wide Si (gray)/SiGe (purple) layer stack. In this way, the Si "seed crystal" beneath the hard mask can support epitaxial growth of the source/drain electrodes The reason why the outer wall forksheet device can achieve fully effective source/drain stress sources is because it adopts the wall last method. Before making the wall, the hard mask will continue to cover the middle portion of the wide Si/SiGe stack, which will later be used to form the wall (Figure 6). The 'Si spine' beneath this hard mask can now serve as a seed crystal during source/drain epitaxial growth, acting as a silicon 'template' that extends from one gate channel to the next. This is similar to Si subfin in FinFET technology: imagine rotating the source/drain epitaxial module 90 ° (Figure 7). If there is no such silicon crystal template, vertical defects will form at the source/drain epitaxial interface, thereby eliminating the compressive strain formed in the silicon channel. Figure 7- The Si spine (right) in the outer wall fork sheet provides a continuous silicon crystal template from one gate channel to the next. This is conceptually similar to Si subfin in FinFET technology (left) External wall forksheet in SRAM and ring oscillator design Finally, IMEC conducted a benchmark study to quantify the power performance area (PPA) advantage of the outer wall fork sheet. When comparing the area of the A10 outer wall fork sheet and the SRAM bit cell based on A14 nanosheets, the area advantage of the nanosheet architecture becomes apparent. Layout display shows that the SRAM cell area based on the outer wall fork sheet has decreased by 22%, due to the reduction in the spacing between pp and nn on the basis of the reduction in gate spacing. Another key indicator for performance evaluation is the simulated frequency of the ring oscillator, expressed as the ratio of effective driving current to effective capacitance (I eff/C eff). Simulation shows that for node A10, an outer wall fork is required to maintain frequency consistency with the previous A14 and 2nm nodes, provided that all of these device structures can achieve full channel stress. It has been proven that achieving full channel stress in nanosheets (2nm and A14) and inner wall fork sheet devices is challenging, and its absence results in a drive current loss of approximately 33%. Therefore, it is expected that the ability to implement an effective source/drain stressor in the outer wall fork sheet device will result in further performance advantages in the design of ring oscillators. Figure 8- Simulation results of ring oscillator (with and without backend (BEOL) load) Outlook and Conclusion The fork blade device architecture was introduced by IMEC with the aim of extending the logic technology roadmap based on nanosheets to the A10 technology node and expecting CFET to achieve mass production. Due to manufacturability issues, IMEC abandoned the original inner wall fork design and developed an "upgraded" version: outer wall fork design. Compared to the inner wall fork sheet, the new design ensures higher manufacturability while improving performance and reducing surface area. Looking ahead to the future, IMEC is currently researching the compatibility between the outer wall forkfoot design and the CFET architecture, as well as to what extent CFET can benefit from PPA from this innovative expansion booster.