In the semiconductor world, some companies rely on technology to make a living, while others rely on patents to make a living. Qualcomm, on the basis of possessing these two, has built a chip empire through targeted "buying and buying". Today, Qualcomm is a chip giant spanning mobile phones, automobiles, the Internet of Things, and AI edge computing. But you may not know that the foundation of this empire is the technology teams and assets that have been quietly swallowed, polished with time and patience. GPU: Adreno Rising from the Afterglow of ATI The graphics processing capability of mobile devices in 2006 can be considered "primitive". At that time, the concept of smartphones had not yet become popular, with BlackBerry and Palm Pilot still dominating the market, and the release of the iPhone had to wait until 2007. In this era of mobile graphics processing where 'running a snake is enough', the vast majority of device manufacturers have extremely limited demand for GPUs, focusing more on basic 2D interface rendering and simple multimedia playback functions. However, it is during this seemingly calm period that a far-reaching technology acquisition is brewing. AMD has decided to acquire ATI Technologies for a sky high price of $5.4 billion in order to gain a graphics processing advantage in competition with Intel. This transaction not only changed the landscape of the PC graphics card market, but also unexpectedly planted an important seed for the mobile graphics processing field. In the AMD-ATI acquisition, AMD's main target was ATI's desktop and server GPU business, while ATI's mobile graphics division was considered a "peripheral" at the time. Although this department has considerable technical strength, the market prospects were not clear at the time. The graphics demand for mobile devices is limited, and the entire industry generally lacks confidence in the development potential of mobile GPUs. However, Qualcomm has demonstrated a forward-looking strategic vision. This company, which started with communication chips, is keenly aware that with the continuous enrichment of mobile device functions, graphics processing capabilities will become one of the core competitiveness of future mobile platforms. When AMD sold ATI's mobile GPU division as a "bundle", Qualcomm was quick witted and quickly acquired this experienced team at a relatively low price. After the acquisition, Qualcomm gave this newly acquired GPU division a memorable name: Adreno. This name is not randomly chosen, but rather a letter rearrangement and combination of ATI's famous GPU brand "Radeon". This naming convention not only reflects respect for ATI's technological heritage, but also symbolizes the team's fresh start under its new owner. The name Adreno itself carries a profound technical background. The Radeon series GPU once competed with NVIDIA's GeForce series in the PC field, with a deep accumulation of graphics processing technology. By preserving the symbolic expression of this technological DNA, Qualcomm is actually declaring to the market that Adreno will continue ATI's technological advantages in the field of graphics processing and further develop them. The original team from ATI has brought valuable technological assets to Adreno. These engineers not only have extensive experience in GPU architecture design, but more importantly, they have a deep understanding of various aspects of the graphics rendering pipeline, from vertex processing to pixel shading, from texture mapping to anti aliasing techniques. With the advent of the smartphone era, Adreno has ushered in its own shining moment. Qualcomm has deeply integrated Adreno into the Snapdragon system on chip platform, forming a collaborative optimization of components such as CPU, GPU, DSP, and modem. This SoC design concept not only improves overall performance, but more importantly achieves better power control and thermal management. The development history of Adreno series GPUs can be seen as a microcosm of the progress in mobile graphics processing technology. From the early Adreno 200 series to the current Adreno 740 series, each generation of products has achieved significant improvements in performance, power consumption, and feature support. Especially in terms of support for graphics APIs such as OpenGL ES, Vulkan, DirectX, Adreno has always maintained an industry-leading level. Today, Adreno has far exceeded the technological scope of ATI's mobile GPU. Modern Adreno GPUs not only support traditional 3D graphics rendering, but also integrate cutting-edge technologies such as machine learning acceleration, computational shaders, and variable rate shading (VRS). Adreno has demonstrated strong adaptability and scalability in emerging fields such as AR/VR applications, computational photography, and AI image processing. From a small team in the ATI laboratory to the graphics processing engine that supports billions of mobile devices worldwide today, Adreno's story can be considered a legend in the history of technology. The spark left by ATI, under the careful cultivation of Qualcomm, ultimately ignited the entire sky of mobile graphics processing. CPU: The confidence to invest in self-developed cores In the world of chip design, there is an unwritten rule: when giants start to feel threatened, real change is about to begin. In 2020, when Apple released the MacBook with the M1 chip, the entire industry was shocked. This is not only because M1's performance is stunning, but more importantly, it has proven a truth to the world: based on mobile chips, it is entirely possible to create products that can rival or even surpass traditional x86 processors. In this shock, the one who felt the deepest was none other than Qualcomm. As the dominant player in the field of mobile chips, Qualcomm suddenly found itself facing unprecedented challenges. Apple is no longer satisfied with dominating only in the fields of smartphones and tablets, but has extended its tentacles to the PC market - a field that Qualcomm has always wanted to enter but has never succeeded in breaking through. For a long time, Qualcomm's Snapdragon processors have relied on the Cortex series public core provided by Arm. This model was indeed effective in the early development stages of the mobile market: Arm was responsible for providing mature and stable architecture design, while Qualcomm and other vendors focused on system level optimization and integration. This division of labor cooperation has enabled the rapid development of the Android ecosystem and also contributed to Qualcomm's leadership position in the mobile chip field. However, as the demand for mobile computing continues to increase, this pattern of relying on public architecture is beginning to expose significant limitations. Firstly, the degree of differentiation is limited. When everyone uses the same CPU core, the differences between products are mainly reflected in the process technology, frequency tuning, and integration of peripheral components. It is difficult to form the architectural advantages of the core. Secondly, the space for performance optimization is limited, and the public architecture must take into account the needs of all authorized vendors, making it difficult to conduct in-depth optimization for specific application scenarios. The most fatal thing is that the success of Apple's M-series chips has shown the industry the enormous potential of self-developed architectures. Apple has achieved breakthroughs not only in performance, but more importantly, in power consumption control through completely autonomous architecture design. The advantage of integrating software and hardware has put unprecedented pressure on manufacturers who rely on public architecture. Faced with the impact of Apple's M-series chips, the entire industry has begun to rethink its architecture strategy. Intel is striving to advance its hybrid architecture design, AMD is continuously optimizing its Zen series architecture, and within the Arm ecosystem, major vendors are also seeking more autonomy. As a leader in mobile chips, Qualcomm is deeply aware of the urgency of change. There is a consensus within the company that if we continue to rely entirely on Arm's public core, it will not only be difficult to compete with Apple in terms of performance, but more importantly, we will lose our dominant position in the next round of technological competition. Especially in AI computing, edge computing and other emerging fields, the flexibility and optimization space of self-developed architecture will become a decisive advantage. In January 2021, Qualcomm announced its acquisition of Nuvia for $1.3 billion, which caused a huge shock in the industry. For many people, Nuvia is still a relatively unfamiliar name - this two-year-old startup has less than a hundred employees, neither mass-produced products nor mature business models. The valuation of $1.3 billion was indeed astonishing at the time. However, Qualcomm is not interested in the current situation of Nuvia, but in its technological strength and development potential behind it. The founding team of Nuvia can be described as luxurious: CEO Gerard Williams III was once the chief architect of Apple's A-series chips, involved in the design of multiple generations of processors from A7 to A12X; CTO Manu Gulati and Chief System Architect John Bruno also have extensive experience in designing high-performance processors. This team not only deeply participated in the golden age of Apple chips, but more importantly, they have a unique understanding of how to create high-performance low-power processors. Nuvia's technological roadmap is also highly aligned with Qualcomm's strategic goals. This company focuses on the development of high-performance Arm processors for data center and edge computing, and its design philosophy emphasizes to achieve maximum performance output while maintaining low power consumption. Although the company has not been established for a long time, its technical team has demonstrated impressive design capabilities in a short period of time. More importantly, Nuvia has complete self-developed CPU core design capabilities. From optimizing instruction set architecture, to innovating microarchitecture, to developing compilers and software stacks, Nuvia possesses full stack technical capabilities. This is exactly the core capability that Qualcomm urgently needs. After the acquisition, Qualcomm did not rush to quickly productize Nuvia's technology, but chose a more secure strategy of deep integration. The core technology team of Nuvia has been fully integrated into Qualcomm's research and development system, becoming an important component of Qualcomm's CPU design department. This integration is not just about merging personnel, but also a deep integration of technical concepts and design methodologies. During the integration process, Qualcomm demonstrated considerable patience and strategic determination. The company did not rush to launch transitional products, but gave the Nuvia team sufficient time and resources to steadily advance according to the established technology roadmap. At the same time, Qualcomm will also combine its rich experience in the field of mobile chips, including knowledge in power management, thermal design, manufacturing processes, etc., with Nuvia's high-performance design philosophy. On the basis of Nuvia technology, Qualcomm has begun to re plan its high-performance CPU core development roadmap. This is not only a technical adjustment, but also a significant transformation of the entire product strategy. The new development roadmap places greater emphasis on balancing and optimizing performance and power consumption. Drawing on Nuvia's experience in high-performance processor design, Qualcomm has begun exploring more radical architectural innovations, including wider execution units, deeper pipelines, and smarter branch prediction. At the same time, based on Qualcomm's experience in power control in the field of mobile chips, the new architecture design also pays more attention to dynamic power management under different workloads. In terms of application scenarios, the new roadmap also reflects stronger targeting. In addition to traditional mobile applications, emerging scenarios such as PC computing, edge AI, and cloud native applications have become key optimization targets. This multi scenario optimization strategy provides technical support for Qualcomm's expansion in different markets. In 2024, Qualcomm officially released the Oryon CPU core based on Nuvia technology, marking the first significant achievement in the three-year acquisition of Nuvia. The release of Oryon not only marks Qualcomm's official entry into the era of self-developed CPU cores, but more importantly, injects new vitality into the entire Arm ecosystem. From the technical specifications, the Oryon CPU has indeed demonstrated impressive performance. While maintaining relatively low power consumption, Oryon's single core and multi-core performance have reached industry-leading levels. Especially in terms of AI workloads, Oryon has achieved significant performance improvements through specialized optimization design. The impressive performance of the Oryon CPU is attributed to its innovative breakthroughs in multiple technological aspects. These innovations not only demonstrate the technical strength of the Nuvia team, but also showcase Qualcomm's profound expertise in system level optimization. In terms of microarchitecture design, Oryon adopts a wider execution engine and a deeper out of order execution queue, which can better explore instruction level parallelism. Meanwhile, Oryon has made significant progress in reducing memory access latency through improved branch prediction algorithms and a larger cache hierarchy. In terms of power management, Oryon inherits Qualcomm's rich experience in the field of mobile chips. By finely dividing power domains and dynamically adjusting voltage and frequency, Oryon is able to dynamically adjust power consumption based on actual workloads, maximizing battery life while ensuring performance. In terms of AI acceleration, Oryon integrates specialized matrix operation units and vector processing units, which can efficiently execute various machine learning workloads. This hardware acceleration capability provides strong support for Oryon based devices in AI applications. The launch of the Oryon CPU has also opened up new market opportunities for Qualcomm. The Snapdragon X series processors equipped with Oryon directly target the PC market, competing head-on with Intel and AMD's traditional advantage areas. At the same time, Oryon also provides strong technical support for Qualcomm's layout in emerging markets such as edge computing and AI reasoning. The acquisition price of 1.3 billion US dollars did raise many doubts at the time, but now it seems that the strategic value of this investment has been fully reflected. Nuvia not only brought a world-class CPU design team and core technology to Qualcomm, but more importantly, won the initiative in the next round of technology competition. Wi Fi/Bluetooth: The 'invisible wings' behind Atheros Atheros, once a pioneer in wireless communication, has now become a part of the Qualcomm empire, but its technological DNA still quietly flows through billions of devices. From the initial laptop Wi Fi card to the connection module in today's smartphones, Atheros' technological heritage spans the entire development process of wireless communication era. To understand the value of Atheros, we must return to the starting point of wireless communication technology. In 1998, when the Wi Fi standard was just established and most people were still using dial-up internet, Atheros had already keenly perceived the enormous potential of wireless communication. This company, founded by a research team from Stanford University, has been focused from the beginning on a seemingly simple but extremely complex problem: how to achieve efficient and stable wireless connections between devices. In that era, wireless communication technology was still in its very early stages. The 802.11a/b standard has just been released, with a transmission rate of only 11Mbps and limited connection stability. But Atheros engineers saw the infinite possibilities of this technology and began to delve into various technical aspects such as RF design, antenna technology, signal processing algorithms, etc., attempting to break through the technological bottleneck of wireless communication at that time. The first major breakthrough of Atheros came from the deep optimization of OFDM (Orthogonal Frequency Division Multiplexing) technology. Although this technology has great advantages in theory, it faces many challenges in practical applications, including signal synchronization, inter carrier interference, power consumption control, and other issues. Atheros engineers have successfully solved these technical challenges through innovative algorithm design and hardware optimization, laying the foundation for the rapid development of Wi Fi technology in the future. The key to Atheros standing out in the fierce market competition lies in its continuous investment and breakthroughs in technological innovation. The company has established a development strategy of "technology oriented" since its inception, investing a large amount of resources into the research and development of core technologies. After the release of the 802.11g standard, Atheros was the first to launch a chip solution that supports a transmission rate of 54Mbps, far exceeding its competitors at the time. More importantly, Atheros' chips perform well in power control and signal stability, which enables devices using Atheros chips to provide longer battery life and more reliable connection experience. With the introduction of the 802.11n standard, MIMO (Multiple Input Multiple Output) technology has become an important direction for the development of Wi Fi. Atheros has once again demonstrated its technological innovation capabilities by launching the industry's first commercial chips that support MIMO technology. Through the application of multi antenna technology, Atheros' solution not only significantly improves transmission speed, but also significantly enhances signal coverage and anti-interference capability. During this process, Atheros has accumulated a wealth of RF design experience and signal processing technology. The company's engineers have conducted in-depth research on various complex wireless environments, from residential homes to corporate offices, from dense urban environments to open rural areas, and developed corresponding optimization solutions for different application scenarios. With its strong technical capabilities, Atheros has gradually established its position in the market. The company's first significant breakthrough came from the laptop market. In the era when Wi Fi technology was just emerging, laptops were the most important application carriers, and Atheros, with its excellent chip performance and stability, successfully gained the favor of many laptop manufacturers. With the popularization of home broadband, the consumer router market has begun to develop rapidly. Atheros keenly seized this opportunity and launched a chip solution specifically designed for router applications. These chips not only support higher transmission rates, but also have stronger concurrent processing capabilities, which can provide stable connection services for multiple devices simultaneously. In addition to the consumer market, Atheros has also achieved significant success in the field of enterprise wireless communication. Enterprise level applications have more stringent requirements for wireless communication, and Atheros has launched specialized chip solutions for the enterprise market. These products have reached industry-leading levels in RF performance, concurrent processing capabilities, security encryption, and other aspects. Many enterprise network equipment manufacturers have adopted Atheros' chips to build their enterprise level access points (APs) and wireless controller products. Although Atheros initially started with Wi Fi technology, the company quickly realized that the limitations of a single technology were evident in the field of wireless communication. Different application scenarios require different connectivity technologies, and companies that can provide comprehensive connectivity solutions can gain the greatest advantage in market competition. Based on this understanding, Atheros began to expand into the field of Bluetooth technology. Although Bluetooth technology is not as good as Wi Fi in terms of transmission distance and speed, it has unique advantages in low power consumption and point-to-point connections, making it particularly suitable for applications such as audio transmission and input device connections. Atheros' Bluetooth chip solution also demonstrates excellent technical standards. The company's engineers have conducted in-depth research on various levels of the Bluetooth protocol stack, from the lower level RF design to the upper level application protocols, all of which have been deeply optimized. This enables Atheros' Bluetooth chip not only to have better audio transmission quality, but also to support more device connections and richer application functions. With the rise of smartphones and other mobile devices, modular connectivity solutions have become the mainstream demand in the market. Atheros timely launched a Wi Fi/Bluetooth combination chip, integrating the two technologies into a single chip, which not only reduces costs and power consumption, but also simplifies the design complexity of devices. However, at this time, the entire wireless communication market underwent fundamental changes. The requirements for connecting chips in mobile devices are completely different from those in traditional PC products: smaller size, lower power consumption, higher integration, and stricter cost control. This is undoubtedly a huge challenge for Atheros, which is mainly focused on the PC market. Just as Atheros faced challenges in its transition to the mobile age, Qualcomm emerged. In January 2011, Qualcomm announced the acquisition of Atheros for $3.1 billion, which caused a huge shock in the industry. For many observers, this acquisition price seems too high, especially considering the market challenges faced by Atheros at the time. However, Qualcomm's strategic vision was fully reflected in this acquisition. Qualcomm has a deep understanding of the development trend of the mobile Internet era, and recognizes that connectivity technology will become one of the key elements of mobile device competitiveness. Although Qualcomm has taken a dominant position in the cellular communication field, its strength in non cellular connection technologies such as Wi Fi and Bluetooth is relatively limited. The value of Atheros lies not only in its existing products and market position, but more importantly, its profound technical accumulation and experienced engineering team. Qualcomm values Atheros' core capabilities in RF design, signal processing, protocol stack optimization, and other areas, which complement Qualcomm's cellular communication technology perfectly. In addition, Qualcomm has also seen a trend towards the integration of connectivity technologies. In mobile devices, Wi-Fi、 Multiple connectivity technologies such as Bluetooth and cellular communication need to work together, and manufacturers that can provide unified optimization will have significant competitive advantages. By acquiring Atheros, Qualcomm not only gained world-class connectivity technology, but also laid the foundation for its comprehensive layout in the mobile communication field. After the acquisition, Qualcomm did not simply operate Atheros as an independent business unit, but chose a strategy of deep integration. This integration is not only reflected in the technical aspect, but also in the integration of culture and organizational structure. In terms of technology integration, Qualcomm has deeply integrated Atheros' connectivity technology with its own mobile processor technology. This integration is not simply physical splicing, but collaborative optimization at various levels such as architecture design, power management, and signal processing. Through this deep integration, Qualcomm can provide customers with better performance, lower power consumption, and more cost-effective connectivity solutions. In terms of organizational structure, Qualcomm has retained Atheros' core technology team and given them full autonomy to continue technological innovation. At the same time, Qualcomm has organically integrated Atheros engineers with its own R&D team, forming a complete technology chain covering from RF to applications. This deep integration strategy has achieved significant results. The Atheros technology team not only maintains its original innovative vitality, but also gains greater development space on the Qualcomm platform. And Qualcomm has greatly enhanced its strength in the field of connectivity technology through this integration. By acquiring Atheros, Qualcomm has successfully achieved a comprehensive layout in the field of wireless connectivity. Nowadays, Qualcomm is the only company in the world that can simultaneously operate in cellular Wi-Fi、 The company that provides top-level solutions among the three major wireless protocols of Bluetooth. This comprehensive technological capability provides solid support for Qualcomm's dominant position in the mobile communication market. In the smartphone market, almost all mainstream Android devices adopt Qualcomm's connectivity solutions. From the Samsung Galaxy series to Chinese brands such as Xiaomi, OPPO, Vivo, and from high-end flagships to mid to low end products, Qualcomm's connectivity technology is ubiquitous. The achievement of this market coverage is largely attributed to the contribution of Atheros technology. In the PC market, although Intel dominates in processors, Qualcomm also has strong competitiveness in Wi Fi connectivity. Many laptops using Intel processors have chosen Qualcomm's solutions for their Wi Fi modules. In the IoT and smart home markets, Qualcomm's connectivity technology has been widely applied. From smart speakers to smart home appliances, from industrial IoT to smart cities, Qualcomm's connectivity solutions provide reliable technical support for various application scenarios. One of the greatest values of Qualcomm's acquisition of Atheros is the unified optimization of multiple connectivity technologies. In modern mobile devices, cellular Wi-Fi、 Multiple connection technologies such as Bluetooth require collaborative work, while traditional separated designs often lead to issues such as increased power consumption, decreased performance, and poor user experience. By deeply integrating Atheros technology, Qualcomm has achieved unified design and optimization of multi connectivity technology. In the Snapdragon platform, various connectivity technologies share underlying resources such as RF front-end, antenna system, power management, etc., which not only reduces costs and power consumption, but also improves overall performance. If mobile chips are Qualcomm's signature, then connectivity technology is its invisible wing. By acquiring Atheros, Qualcomm not only gained world-class connectivity technology, but more importantly, completed its strategic transformation from a mobile chip manufacturer to a comprehensive communication solution provider. V2X and Vehicle Regulations Blueprint: Autotalks adds the finishing touch In the tide of intelligent driving, the "dialogue" between vehicles is moving from dreams to reality. The communication between vehicles (V2V) and between vehicles and infrastructure (V2I) together form the foundation of V2X (Vehicle to Everything) technology. These 'invisible dialogues' will become a key support for the safety and synergy of autonomous driving, and are a more' far sighted 'warning system than radar and cameras. Qualcomm has long regarded cars as the next highland of mobile Internet. From the Snapdragon Cockpit platform to the Snapdragon Ride positioning autonomous driving control platform, Qualcomm has built a multi-level automotive SoC system covering information entertainment, AI decision-making, sensor fusion, and more. However, what has been missing in this entire solution is the 'last mile' of V2X communication, a key technology. To this end, Qualcomm acquired the Israeli company Autotalks. This company has been deeply involved in the V2X chip field for many years and is one of the few chip manufacturers that can support both DSRC (Dedicated Short Range Communication) and C-V2X (Cellular Connected Vehicle Communication) dual protocols, with customers spread throughout the European and American automotive supply chains. Compared to the slow exploration of self-developed by major manufacturers, Autotalks' technology has been honed and matured through field testing and on-board processes, with the practical advantage of plug and play implementation. In 2023, this acquisition was quickly completed, and Qualcomm thus established a complete link from intelligent cockpit and autonomous driving control to the connection between the vehicle and the outside world. In the Snapdragon Ride platform, Qualcomm has integrated V2X modules natively for the first time, rather than providing them as external chips. This system level integration not only brings about power optimization and cost control, but more importantly, enhances the stability and synergy of V2X in the entire vehicle system, especially opening up new paths in the integration of AI and V2X information at the vehicle end. On a deeper level, this acquisition is not only a 'technological reinforcement', but also a bet on the future intelligent transportation landscape. Driven by 5G, the connection between cars and everything is no longer an isolated system, but an ecosystem of collaborative perception and decision-making. Whoever can occupy a pivotal position in this network holds the discourse power of "swarm intelligence" in autonomous driving. Autotalks is like a finishing touch to Qualcomm. It not only fills a technological gap, but also elevates Qualcomm's "vehicle specification blueprint" from single machine intelligence to collaborative intelligence - from in car intelligent systems to active cognition of the outside environment. This marks another crucial step for Qualcomm from being a "smart car chip supplier" to a "leader in intelligent transportation platforms". SerDes: The behind the scenes player in laying out high-speed interconnectivity If AI chips are powerful "factories" of computing power, then the data flowing between them is the "blood" that maintains the efficient operation of the entire system. What truly determines whether this blood can circulate efficiently is the often overlooked "data highway" - SerDes (serial parallel converter) technology. With the rapid development of AI reasoning, edge computing, automotive electronics and data center, data interconnection capability has become a new bottleneck of SoC system. The delay and bandwidth of data transmission, whether between internal modules of chips or between chips, often directly determine the performance limit of the entire platform. Qualcomm, which has always been known for its expertise in radio frequency and communication, realized early on that high-speed interconnection would be the key infrastructure that would determine the outcome in the process of advancing towards AI and data centers. But this is not Qualcomm's traditional strength. Faced with this "niche but crucial" technological gap, Qualcomm did not choose to develop from scratch, but instead took decisive action and quietly acquired some SerDes assets of Canadian technology company Alphawave Semi. Although not as well-known as some major manufacturers, Alphawave is a star company in the high-performance SerDes IP field, particularly skilled in high-speed interface solutions under various protocol standards such as PCIe, CXL, Ethernet, etc. Its technology enables high-speed transmission of data in a narrow physical channel with low power consumption and low bit error rate, which is crucial for cutting-edge SoC architectures such as processes below 5nm, Chiplet packaging, and multi Die interconnects. Through this acquisition, Qualcomm has quietly completed a "remedial lesson" in its high-speed I/O IP layout. Its strategic significance goes far beyond enhancing the data transmission capabilities of existing SoCs, but also focuses on the "underlying preparation" for Qualcomm's future entry into new battlefields such as data centers, AI acceleration cards, Chiplet heterogeneous computing platforms, etc. Especially in today's Chiplet trend, a single large chip is gradually being replaced by a combination of multiple small chips (Die), and the high-speed interconnection capability between chips has become a watershed for the success or failure of the platform. Without mature SerDes technology, Chiplets are like a puzzle that cannot be pieced together. With Alphawave's technological capabilities, Qualcomm can not only break through the internal "bottlenecks" of SoCs, but also build its own efficient modular platform architecture in the Chiplet era. More importantly, this interconnection capability is no longer limited to "internal optimization". It has become a bridge for Qualcomm to build the next generation of AI and communication fusion systems - whether it is the AI inference card on the server side or the collaborative work of different modules in the vehicle platform, SerDes technology is an irreplaceable "critical channel". In this competition over speed, latency, power consumption, and area, Qualcomm has quietly upgraded itself from a "chip company" to a "system interconnect layout provider" with a precise move. At the critical juncture of transitioning from the era of chips to the era of system integration, SerDes technology, this small screw, is supporting Qualcomm's next round of ambitions. At the end: What I bought is not only technology, but also the future The outside world often says that Qualcomm is a technology company, but in fact, it is more like the best example of capital and technology integration. Each of its core capabilities - graphics CPU、 Wireless communication, V2X, SerDes - almost all originated from strategic mergers and acquisitions. But what truly takes root and sprouts these abilities is Qualcomm's ability to internalize them into an ecosystem and unify them into a platform. It is not simply assembling parts, but melting them into an organic chip empire. This is a story that reached its peak through mergers and acquisitions, but it's not just about buying. It relies on digestion, integration, and re creation. From mobile phones to cars, from connectivity to computing, Qualcomm has made precise attacks time and time again, writing the legendary semiconductor empire that was "bought". As you can see, the foundation of the empire may have been bought, but tall buildings were built brick by brick.

The main feature of GAA nanosheet devices is the vertical stacking of two or more nanosheet conductive channels, with each logic standard cell containing one stack for p-type devices and another stack for n-type devices. This configuration allows designers to further reduce the height of logical standard cells, defined as the number of metal lines (or tracks) per cell multiplied by the metal spacing. Designers can also choose to widen the channel at the expense of sacrificing unit height for larger driving current. In addition to the reduced area, GAA nanosheet transistors have another advantage over FinFETs: the gate surrounds the conductive channel from all directions, enhancing the gate's control over the channel even at shorter channel lengths. Figure 1- TEM image of GAA nanosheet device GAA nanosheet technology is expected to continue for at least three generations before chip manufacturers transition to CFET (complementary FET) technology. Due to its nMOS pMOS vertical stacking structure, the integration complexity of CFET is significantly higher than that of conventional nanosheet devices. According to IMEC's roadmap, the mass production of CFET is only feasible starting from node A7. This means that the era of GAA nanosheets must extend at least to the A10 technology node, where the unit height is expected to be as small as 90 nanometers. However, reducing the standard cell size based on GAA nanosheets without affecting performance is extremely challenging. This is exactly where forksheet device architecture may bring relief, as it is a non-destructive technology with greater scalability potential than conventional GAA nanosheet technology. Forksheet, 1nm reliance In 2017, IMEC launched the forksheet device architecture, first as a scaling booster for SRAM cells, and later as a scaling enabler for logic standard cells. The unique feature of its first implementation is the placement of a dielectric wall between nMOS and pMOS devices before gate patterning. Due to the fact that this wall is located in the middle of the logical standard unit, the architecture is referred to as an "inner wall" fork sheet. The wall physically isolates the p-gate trench from the n-gate trench, achieving a tighter n-to-p spacing than FinFET or nanosheet devices. This allows for further reduction of unit area (unit height up to 90nm) while still providing performance improvement. In this' inner wall 'configuration, these thin sheets are controlled by a tri gate forked structure, hence the name of the device. Figure 2- TEM image of the inner wall fork device At VLSI 2021, imec demonstrated the manufacturability of the 300mm inner wall fork sheet process flow. Conducting electrical characteristic tests on fully functional devices confirms that forksheet is the most promising device architecture, capable of extending the miniaturized roadmap of logic and SRAM nanosheets to the A10 node. Due to the reuse of most of the production steps of nanosheets in the integrated process, the technological evolution from nanosheets to forksheets can be considered non disruptive. Manufacturability is being challenged Despite the successful hardware demonstration, some concerns about manufacturability still exist, which has led IMEC to reconsider and improve its initial fork sheet device architecture. The main challenge is related to the manufacturability of the inner wall itself. In order to achieve a 90nm logic standard cell height, the dielectric wall needs to be very thin, within the range of 8-10nm. However, due to the early manufacturing of the equipment process, the wall will be exposed to all subsequent front-end process (FEOL) etching steps, which may further reduce the thickness of the wall, placing considerable demands on the selection of wall materials. In addition, in order to achieve process steps specific to n or p (such as p/n source/drain epitaxy), dedicated masks must be precisely placed on thin dielectric walls, which poses a challenge to the alignment of p/n masks. In addition, 90% of devices in practical applications have a common gate for n and p channels. In standard cells with inner wall forksheet devices, dielectric walls can hinder the pn connection gate. Unless the gate is made higher to cross the wall, which would increase parasitic capacitance. Finally, chip manufacturers are concerned about the three gate architecture, as the gate only surrounds the channel from three sides. Compared with the GAA structure, there is a risk of losing control over the channel at the gate, especially when the channel length is short. External wall fork: dielectric wall at the boundary of CELL At the Very Large Scale Integration Technology and Circuit Symposium 2025 (VLSI 2025), researchers from imec presented a novel fork sheet device architecture and named it the "outer wall fork sheet". They demonstrated through TCAD simulation how this outer wall forksheet improves its previous design by reducing process complexity, providing excellent performance, and maintaining area scalability. Figure 3- Imec's logical technology roadmap, showing the extension of the nanosheet era from 2nm to A10 node, using outer wall forksheet, and then transitioning to A7 and higher versions of CFET The outer wall forksheet places the dielectric wall at the boundary of the standard cell, making it a pp or nn wall. This allows each wall to be shared with adjacent standard cells and can be thickened (up to about 15 nanometers) without affecting the height of the 90 nanometer cells. Another significant feature is the wall cast integration method. The entire process begins with the formation of a wide Si/SiGe stack - a step that is repeated in any GAA technology. After etching away SiGe in the nanosheet channel release step, the stacked Si layer will form nanosheet shaped conductive channels. The dielectric wall will eventually divide the stack into two, with two FETs of similar polarity located on either side of the wall. The dielectric wall itself is processed towards the end of the integration process, that is, after the channel release of the nanosheets, source/drain etching, and source/drain epitaxial growth. The step of replacing the metal gate (RMG) has completed the integration process. Figure 4- Schematic diagram of the forksheet structure for the (top) inner wall and (bottom) outer wall 5 key improvements to the outer wall forksheet Compared with GAA nanosheet devices, inner and outer wall forksheets have two common advantages. In terms of area scaling, they are all able to achieve a 90nm logical standard cell height at the A10 node, which is more advantageous compared to the 115nm cell height in A14 nanosheet technology. The second common advantage is the reduction of parasitic capacitance: the two field-effect transistors (FETs) located on both sides of the wall (with n and p on the inner wall and n and n/or p and p on the outer wall) can be placed closer than units based on nanosheets without causing capacitance problems. In addition, the outer wall forks are expected to surpass the inner wall forks in five key aspects of design. Firstly, due to the adoption of the wall last integration method, the dielectric wall eliminates several complex FEOL steps. Therefore, it can be made from mainstream silica. In the back wall process step, walls are formed by forming trenches in a wide Si/SiGe stack and filling them with SiO2 dielectric. Secondly, as the wall is located at the boundary of the unit, its width can be relaxed to about 15nm, thereby simplifying the process. Thirdly, it is now easy to connect the gates of n and p devices within a standard cell without passing through dielectric walls. Fourthly, the outer wall forksheets are expected to provide better gate control than the inner wall devices, which is related to their ability to form Ω - gate structures instead of three gate forksheets. A wider dielectric wall makes it possible to etch the wall several nanometers in the final RMG step. This allows the gate to partially surround the fourth edge of the channel, forming a W-shaped gate and enhancing control over the channel. Through TCAD simulation, imec researchers found that etching off the 5-nanometer dielectric wall is the best choice, which can increase the driving current by about 25%. Figure 5- The effect of wall etching on gate formation: from triple gate to Ω gate, and then to GAA The fifth aspect is related to the potential of forksheet integrated flow to provide full channel strain, which is an additional performance improvement that is beneficial for driving current. Usually, full channel strain can be obtained by implementing source/drain stress sources. This method has been proven to be highly effective in (p-type) FinFETs, but it is difficult to implement in GAA nanosheets and inner wall forksheet device architectures. Conceptually, the idea is to incorporate Ge atoms into the source/drain regions. Due to the larger size of Ge atoms compared to Si atoms, they introduce compressive strain in the Si channel, thereby increasing the mobility of charge carriers. Figure 6- At the beginning of the outer wall fork sheet process, a "pre all" hard mask (brown) is deposited on top of a wide Si (gray)/SiGe (purple) layer stack. In this way, the Si "seed crystal" beneath the hard mask can support epitaxial growth of the source/drain electrodes The reason why the outer wall forksheet device can achieve fully effective source/drain stress sources is because it adopts the wall last method. Before making the wall, the hard mask will continue to cover the middle portion of the wide Si/SiGe stack, which will later be used to form the wall (Figure 6). The 'Si spine' beneath this hard mask can now serve as a seed crystal during source/drain epitaxial growth, acting as a silicon 'template' that extends from one gate channel to the next. This is similar to Si subfin in FinFET technology: imagine rotating the source/drain epitaxial module 90 ° (Figure 7). If there is no such silicon crystal template, vertical defects will form at the source/drain epitaxial interface, thereby eliminating the compressive strain formed in the silicon channel. Figure 7- The Si spine (right) in the outer wall fork sheet provides a continuous silicon crystal template from one gate channel to the next. This is conceptually similar to Si subfin in FinFET technology (left) External wall forksheet in SRAM and ring oscillator design Finally, IMEC conducted a benchmark study to quantify the power performance area (PPA) advantage of the outer wall fork sheet. When comparing the area of the A10 outer wall fork sheet and the SRAM bit cell based on A14 nanosheets, the area advantage of the nanosheet architecture becomes apparent. Layout display shows that the SRAM cell area based on the outer wall fork sheet has decreased by 22%, due to the reduction in the spacing between pp and nn on the basis of the reduction in gate spacing. Another key indicator for performance evaluation is the simulated frequency of the ring oscillator, expressed as the ratio of effective driving current to effective capacitance (I eff/C eff). Simulation shows that for node A10, an outer wall fork is required to maintain frequency consistency with the previous A14 and 2nm nodes, provided that all of these device structures can achieve full channel stress. It has been proven that achieving full channel stress in nanosheets (2nm and A14) and inner wall fork sheet devices is challenging, and its absence results in a drive current loss of approximately 33%. Therefore, it is expected that the ability to implement an effective source/drain stressor in the outer wall fork sheet device will result in further performance advantages in the design of ring oscillators. Figure 8- Simulation results of ring oscillator (with and without backend (BEOL) load) Outlook and Conclusion The fork blade device architecture was introduced by IMEC with the aim of extending the logic technology roadmap based on nanosheets to the A10 technology node and expecting CFET to achieve mass production. Due to manufacturability issues, IMEC abandoned the original inner wall fork design and developed an "upgraded" version: outer wall fork design. Compared to the inner wall fork sheet, the new design ensures higher manufacturability while improving performance and reducing surface area. Looking ahead to the future, IMEC is currently researching the compatibility between the outer wall forkfoot design and the CFET architecture, as well as to what extent CFET can benefit from PPA from this innovative expansion booster.