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In the early stages of fierce competition, Samsung grew rapidly with fierce attacks, making TSMC Chairman Morris Chang consider it a formidable competitor. However, history is always full of variables. In recent years, Samsung has encountered setbacks in multiple fields, not only failing to catch up with TSMC in wafer foundry business, losing its dominance in DRAM to South Korean rival SK Hynix, but also facing major setbacks in advanced process yield. The latest news is that the Texas factory has been delayed in opening. In terms of wafer foundry business, Samsung has repeatedly failed to block TSMC. The yield rate of 3nm is only about 50%, lagging behind TSMC in 2nm yield rate. 4nm orders have been taken away by TSMC, and 5/7nm orders have also been shared by Chinese manufacturers. Samsung has significantly adjusted its strategy by delaying the production time of the 1.4nm process, temporarily withdrawing from the competition for advanced processes, and instead improving the yield of existing processes, providing customized services, and one-stop solutions. However, its wafer foundry business still faces severe challenges, with an operating loss of KRW 4 trillion in 2024 and an expected full year loss of approximately KRW 3 trillion this year. The Texas factory has also decided to postpone its start-up time due to weak market demand and insufficient customers. In the DRAM field, Samsung once dissolved the HBM team due to misjudging the market, resulting in progress lagging behind SK Hynix. In the first quarter of this year, SK Hynix surpassed Samsung with a market share of 36%, becoming the new dominant player in the global DRAM market. Although Samsung plans to launch an enhanced 12 layer HBM3E and produce HBM4 chips and supply samples in the second half of the year in an attempt to regain its throne, the road ahead is difficult. Samsung is facing a low price impact from the Chinese supply chain in terms of panels, LEDs, and traditional DRAM. Chinese manufacturers not only compete for market share at low prices, but also actively poach Korean semiconductor talents. Samsung was forced to shut down its LCD panel production line and switch to OLED and quantum dot panel technology; Exit the LED business and focus on power semiconductors and Micro LED technology; In the traditional DRAM field, DDR4 modules will be discontinued at the end of the year to focus on higher profit products. In the field of mobile phone brands, although Samsung still maintains its leading position in terms of shipment volume and market share, its global smartphone sales ranking in the first quarter of this year was reversed by Apple, and its flagship phone Pixel 10 series also switched to TSMC chips, causing a significant blow to Samsung. Samsung Electronics' semiconductor business is sluggish, with a provisional operating profit of 4.6 trillion Korean won in the second quarter, a year-on-year decrease of 55.94% and a month on month decrease of 31.24%, far below market expectations, and falling below 5 trillion Korean won for the first time in six quarters, hitting a two-year low; Sales amounted to 74 trillion Korean won, with both year-on-year and month on month declines. Affected by AI chip sanctions, decreased inventory and operating rates, departments such as foundry and NAND are experiencing losses, HBM's contribution is low, and wafer foundries may continue to run deficits. The depreciation of the Korean won also adds to the negative impact. The profits of television and home appliances have slowed down, and it is expected that the operating profit of the DS department will be about 1 trillion Korean won, while other departments have their own predictions. The performance may hit bottom in the second quarter, and there is hope for a recovery in the storage business in the second half of the year. Samsung's transition from growth to crisis confirms the warning of its former chairman, Lee Kun hee, that "within ten years, representative businesses and products may disappear, and top tier companies may also collapse. Industrial competition is not only about speed, but also about stability. If Samsung wants to establish a foothold in the new global semiconductor order, it needs to return to the essence of technology, deepen customer relationships, and properly handle geopolitical risks. The next round of competition has begun, and whether Samsung can regain its dominance remains to be verified by time.

In the battlefield of wafer foundry without gunpowder, every iteration of advanced processes touches the nerves of the global technology community. Nowadays, this competition has entered the era of 1.4nm: high research and development costs and strict technological barriers are pushing Moore's Law to its true limits. However, as the semiconductor industry rises to a national strategic level, price is no longer the only consideration. By the way, 1.4nm is often written as 14 A (A=0.1 nm), but node names such as 3nm, 2nm, and even 1.4nm are now more of a "banner" to distinguish between new and old processes, and have long been disconnected from the physical size of actual transistors. As the three major players in the 1.4nm race, TSMC, Intel, and Samsung can be regarded as a large-scale "Three Kingdoms", each laying out their own strategies in the game of performance and technology. However, under the interweaving of multiple pressures such as yield, production capacity, diversified customer demands, and economic investment, this global technology competition among top companies is quietly emerging with differences and variables. Samsung 1.4nm Delay Samsung Electronics, which was originally ambitious, officially announced at the "SAFE Forum 2025" on June 1st that its 1.4nm (14A) semiconductor production target will be postponed to 2029, two years later than previously planned. The construction of the 1.4nm testing line originally scheduled to start in the second quarter of this year has also been postponed, and the investment plan has been postponed until the end of this year or the first half of next year. This is not only one year later than TSMC's 2028 target, but also raises industry concerns about a series of deep-seated issues in Samsung's wafer foundry division. Now, Samsung is one step further away from its dream of becoming the "top semiconductor foundry" by 2030. Why is there a delay? It is widely interpreted that this is Samsung Foundry's strategic move to cope with the current loss situation. It is reported that Samsung's wafer foundry division suffered losses of up to 4 trillion Korean won last year due to the loss of major customers; And in the first quarter of this year, the loss also reached an astonishing 2 trillion Korean won. Faced with performance pressure, Samsung Electronics has decided to focus on immediate process improvements rather than investing heavily in advanced technology. Therefore, Samsung is trying to improve its profitability by increasing the maturity and utilization rate of 2nm or higher processes. Instead of blindly pursuing advanced processes, it is better to first improve the yield of its mass production processes. According to insiders, the manufacturing yield of Samsung's 2nm process is currently about 40%, while TSMC has exceeded 60%, reaching the threshold for stable mass production. It is reported that the 2nm (SF2) process is scheduled for mass production this year as originally planned, with a focus on stabilizing and improving SF2P (second-generation) and SF2X (third-generation) technologies before 2028; At the same time, profitability can be ensured by increasing the operational efficiency of relatively mature processes such as 4nm, 5nm, and 8nm. There are even reports that Samsung has requested its partners to focus on developing relevant IPs to enhance the attractiveness of these processes. In order to ensure the smooth mass production of the Exynos 2600 application processor using a 2nm process, which will be released in the second half of the year, Samsung's Chief Technology Officer (CTO), Nan Xiyu, is personally forming and operating the 2nm Task Force (TF) team. After all, if the yield continues to remain at a low level of 20-30%, even domestic chips cannot guarantee supply. In addition, striving for 2nm orders from large North American technology companies such as Tesla and Qualcomm is also a key factor for Samsung to increase revenue in the future. According to a report by the Central Times, a semiconductor industry source said, "Samsung Electronics' foundries have been focused on competing at cutting-edge nodes, repeatedly entering the next generation of processes under unstable conditions, resulting in a decrease in yield and loss of customer trust. The decision to strengthen the strength of foundries can be seen as a positive measure Intel changes bet on 14A, 18A, where do we go from here On the other hand, Intel's wafer foundry division is also struggling. Recently, Reuters reported that Intel CEO Chen Liwu is considering shifting the focus of wafer foundry to the "14A" chip manufacturing process, while the "18A" process promoted by former CEO Kissinger may face the risk of being cancelled or reduced in priority. 18A was once a "generational leap" for advanced technologies such as RibbonFET and PowerVia, and Intel had high hopes for it. PowerVia is Intel's unique and industry-leading backside power architecture, which can increase standard cell utilization by 5-10% and improve ISO power performance by up to 4%. RibbonFET is a ring gate (GAA) transistor implemented by Intel's foundry, which improves density and performance compared to FinFET. ）Reuters reported that Intel's 18A process is considered to be at the same level as TSMC's 3-nanometer process. Schematic diagram of RibbonFET and PowerVia (source: Intel) Why is there such a change? The customer appeal of 18A is insufficient: Although 18A has won customers such as Amazon and Microsoft, it was initially designed more for Intel's own products, with the goal of increasing production of its "Panther Lake" laptop chips by later 2025. For Intel, which urgently needs to win more external OEM customers such as Apple and Nvidia, the appeal of the 18A seems insufficient. The OEM business urgently needs a breakthrough: Intel's OEM department urgently needs customer orders. Instead of stubbornly fighting on the already "late" 18A, it is better to invest more resources into the more promising 14A process. Financial considerations: The development of 18A has cost billions of dollars, and if the focus is cancelled or reduced, it may result in losses of hundreds of millions of dollars. But in the rapidly changing market, timely stop loss and adjust strategy may be a wiser choice. According to the original plan, Intel's 18A derivative version 18A-P will be released in 2026, and 18A-PT will be released in 2028. According to Wccftech, 18A-PT is particularly noteworthy as it will become Intel's first node to support Foveros Direct 3D hybrid bonding, enabling it to adopt TSMC's advanced interconnect technology. Chen Liwu believes that if Intel wants to compete with TSMC, it can only have an advantage in the 14A process. As early as February last year, Intel included the 14A-E in its advanced process schedule and announced at this year's "Intel Foundry Direct Connect 2025" that it would undergo risk trial production in 2027, with its derivative version 14A-E also planned to be produced in the same year. If this shift in focus comes true, it will be the second consecutive node for Intel to lower its priority, and it is more likely to mean that Intel will "substantially withdraw" from the OEM market in the coming years, with serious consequences.   Technically speaking, the Intel 14A will go further than the 18A by adopting the second-generation surround gate technology RibbonFET 2 and the second-generation back power supply network PowerDirect. In addition, the 14A also uses enhanced cell technology Turbo Cells, which can further improve speed (including CPU maximum frequency and GPU critical path) when used in conjunction with RibbonFET 2. Turbo Cells allow designers to optimize higher performance units and more energy-efficient unit combinations within the design module, achieving a balance between power consumption, performance, and area for the target application. Compared to its predecessor, the performance of the 14A has improved by 15% to 20%, chip density has increased by nearly 30%, and power consumption is expected to decrease by more than 25%. It is worth mentioning that Intel is at the forefront of adopting High NA EUV (high numerical aperture extreme ultraviolet lithography equipment) and has installed a second High NA EUV in Oregon. Intel emphasizes that the 14A is compatible with Low or High NA solutions and has no impact on customer design rules. Despite its strong technological capabilities, Intel still faces numerous obstacles. Competitors such as TSMC and Samsung are actively expanding their own processes, while Intel's annual capital expenditure of over $40 billion to maintain its leading position may strain its balance sheet. The release schedule of the 14A process node in 2026 also depends on whether the yield problem of high numerical aperture EUV lithography machines can be solved. Given ASML's limited supply of such lithography machines, this task is very complex. In addition, the timeline adopted by the client is still uncertain. Although Microsoft's 18A chip is progressing smoothly, major AI companies such as Nvidia and AMD still heavily rely on TSMC. Intel's success depends on whether these companies can believe that its nodes can provide excellent PPAC (power consumption, performance, area, cost) metrics - a statement that must be proven through mass production. Anyway, Intel's 14A/18A roadmap represents its best opportunity to regain leadership in the semiconductor manufacturing industry. Intel can only take a gamble. TSMC steadily operates at 1.4nm As an industry leader, TSMC is the most highly anticipated company to take the lead in 1.4nm. After all, TSMC has demonstrated strong advantages in previous generations of nodes. For example, although Samsung was earlier than TSMC in 3nm, its yield rate was not as good as TSMC's. 3nm did not win more customers for Samsung, but instead lost them. It has been proven that 'the first to submit the paper may not necessarily be the best answer.' For the wafer foundry industry, true leadership lies in mature technology and stable mass production capabilities. A14 is TSMC's second-generation nanosheet transistor, which is considered a full node (PPA) compared to N2. A14 also adopts the innovative standard cell architecture of "NanoFlex Pro" to achieve better performance, energy efficiency, and design flexibility. Speed increases by 10-15% at the same power, power consumption decreases by 25-30% at the same speed, and logic density increases by 1.2 times. TSMC expects A14 to be put into production in 2028, and the development is progressing smoothly with yield achieved ahead of schedule.   It is interesting that TSMC has always maintained a relatively cautious and conservative attitude towards the adoption of new technologies in the research and development of new nodes. The reason is that once multiple new technologies that have not been fully validated and have high risk boundaries are introduced into the process, the "ramp up" period of the yield curve will be significantly prolonged, thereby slowing down the overall speed from trial production to mass production. TSMC's conservative strategy can precisely strike a balance between immature new technologies and large-scale delivery demands, shorten the risk trial production cycle, and quickly seize market share. Specifically, let's take a look: Cost benefit trade-off: The single procurement and maintenance cost of High NA EUV lithography machines is almost 2.5 times higher than that of ordinary NA EUV, requiring additional process debugging and supporting material investment, significantly increasing wafer costs. For A14 chips aimed at the mass consumer market, once High NA EUV is adopted, it will not only cause a sharp increase in manufacturing costs and difficulty in compressing the overall BOM, but may also affect OEM manufacturers' procurement decisions due to high premiums. Yield ramp up and stable delivery: Before sufficient yield validation and controllable risks are achieved for ordinary NA EUV equipment and related supporting facilities, hasty switching can prolong the time window for yield improvement and even lead to delivery delays. TSMC initially did not introduce Backside Power Delivery and Super Power Rail (SPR) on its first generation products such as A14 and N2. After the downstream design toolchain and material ecology are further improved, TSMC will gradually introduce them at improvement nodes such as A16 and A14P to ensure the delivery rhythm of the mainstream market. Targeted by customer group and market positioning: For mainstream nodes such as A14, which are aimed at high-end smartphones and consumer electronics, cost-effectiveness often takes priority over extreme performance; Enhanced processes such as A14P and A16 are more targeted towards servers, AI acceleration cards, and other fields that are extremely sensitive to performance and power consumption and willing to pay a premium. Between technological maturity and market demand, TSMC has achieved the maximization of commercial value through differentiated layout, striving for progress while maintaining stability. Although Zhang Xiaoqiang, Senior Vice President of Business Development at TSMC, has pointed out that High NA EUV has significant value in terms of 1.5D/2D design freedom, process step simplification, and capacity improvement in the field of logic chips (which can bring about a cost-effectiveness increase of about 35%), TSMC is not in a hurry to introduce all cutting-edge technologies into mainstream nodes at once from 2nm to A14 processes. Instead, it chooses to gradually adopt High NA EUV in the A14P process that can afford the cost premium in the future. This not only ensures the controllable cost and stable delivery of mainstream products, but also provides sufficient technical support for higher end applications. summarize According to the timeline, the production of Intel 14A will be in 2027, TSMC in 2028, and Samsung in 2029. In terms of the adoption of High NA EUV lithography machines, Intel is the "first person to eat the crab", TSMC is slightly cautious, and Samsung has not clearly stated whether to use them, only stating that it is evaluating the possibility of using high NA EUV tools in its 1.4nm foundry process. This 1.4nm competition is not only a competition of technological strength, but also a comprehensive consideration of strategic decision-making, market positioning, and profitability. Who can stand out in this advanced process of the "Three Kingdoms"? Let's wait and see!

Recently, there have been rumors in the market that TSMC will withdraw from the gallium nitride (GaN) market, and the related production lines of the wafer fab located in Zhuke have also stopped production. And Navitas, the main customer of TSMC's gallium nitride foundry business, also pointed out that TSMC will end its gallium nitride (GaN) wafer foundry business on July 31, 2027 and intends to seek capacity support from TSMC.   On July 3rd, according to the latest news from TSMC, after a complete evaluation, the company has decided to gradually withdraw from the gallium nitride (GaN) business over the next two years. This decision is based on the long-term business strategy of the market and TSMC. The company is working closely with customers to ensure smooth transition and is committed to continuing to meet customer needs during this period.   TSMC emphasizes that it will continue to focus on creating value for partners and the market, and gradually withdrawing from the gallium nitride business will not affect its previously announced financial goals. TSMC estimates that US dollar revenue will grow by 24% to 26% this year.   TSMC began to enter the field of gallium nitride foundry with 6-inch factories many years ago. In recent years, it has actively invested in the research and development of 8-inch foundry technology, seeking alternative foundry opportunities for 8-inch factories. However, with the intensification of market competition, profits have become increasingly low, and even multiple Taiwanese factories have suffered losses. Therefore, TSMC has strategically chosen to gradually withdraw from the gallium nitride field.   Navitas Semiconductor, an international power semiconductor manufacturer, is a major customer of TSMC's gallium nitride foundry business. With TSMC's exit, Navitas announced a partnership with TSMC to produce gallium nitride (GaN) chips in an 8-inch factory.   Nano Semiconductor stated that TSMC's 8B factory located in Zhunan Science Park will produce gallium nitride products ranging from 100V to 650V for Nano Semiconductor. The first batch of products is expected to be certified in the fourth quarter of 2025. The 100V series products are planned to be put into production at TSMC in the first half of 2026, and the 650V products will gradually be outsourced from the existing supplier TSMC to TSMC in the next 1-2 years.   Industry interpretation shows that gallium nitride (GaN) has limited profit margins and even losses at present, while TSMC's GaN investment scale is relatively small and its profit contribution is limited. Therefore, TSMC has chosen to strategically exit and focus on high gross profit AI logic outsourcing business.

Samsung, SK Hynix, Micron, and domestic manufacturers have successively issued EOL notices for the old process DDR4 with insufficient profits, planning to gradually stop DDR4 shipments in the next two to three quarters, and only maintain limited supply in specific industries such as automobiles and industries that require long-term locking materials. Each DRAM manufacturer needs higher profitability and ROI levels to support the capital expenditures required for the research and development of next-generation advanced DRAM technology, advanced equipment, and capacity expansion, and to occupy market share with leading technological advantages in AI driven industrial upgrading. Therefore, driven by technological iteration, expanding profits, and AI demand, DRAM manufacturers have unanimously focused on migrating to advanced nodes such as 1a/1bnm, while consumer and server DDR4 only stays in old processes such as 1y/1znm, and the supply side relies more on inventory to meet the long-term demand for DDR4. With the continuous expansion of HBM and DDR5 production capacity in advanced processes, the proportion of DDR4 bit output from some original factories in the third quarter decreased to single digit percentages, and the DRAM production capacity of the three major original factories' 1x/1ynm processes will significantly decrease. Due to sufficient supply of processor platforms supporting DDR4/LPDDR4X, there is a severe shortage of supply for DDR4/LPDDR4X. The mid to low end SoC platforms have not yet fully adapted to LP5X. Driven by the recovery of profits from general-purpose DRAM, it is not ruled out that some DRAM manufacturers may consider restoring a certain proportion of LPDDR4X production capacity, in order to prioritize meeting the LPDDR4X needs of some tier 1 mobile phone customers and ensure that the normal shipment of the entire machine is not affected. However, it is expected that the supply of LP4X to other consumer customers will still be very limited, and the supply of LPDDR4X for consumer 2/3/4GB is expected to continue to be scarce. The DRAM production line that has been switched by the original factory is irreversible and may maintain a small amount of DDR4 production capacity based on existing profits, but the current production and supply of DDR4 cannot meet the existing market demand.   Due to DDR5 chips starting from 16Gb capacity, DDR3 is not sufficient to support 8Gb capacity, resulting in a particularly tight supply of 8Gb DDR4 chips. This not only puts significant hardware upgrade pressure on consumer terminals, but also causes a shortage of DRAM chips used in eSSD new orders for DRAM base. The contract price is expected to continue to rise by 30% -40% in the third quarter. Mobile phones: It is expected that the global smartphone shipment volume will remain basically the same year-on-year by 2025, with about 1.2 billion units, ， The demand for LPDDR4X in mobile phones still accounts for a large proportion. After the switch of the original production line, it is expected that there will be an overall supply gap of about 15% to 20% for LPDDR4X in mobile phones, especially for low capacity LPDDR4X of 6GB and below, which is extremely limited and scarce. This has driven a month on month increase of over 20% in LPDDR4X contracts in the third quarter and is approaching the ASP of LPDDR5X. PC: Global PC shipments are expected to increase by approximately 2.8% year-on-year to 261 million units in 2025, with AI PC shipments expected to exceed 90 million units, making AI PC the main growth driver of the PC market. Due to the continuous reduction of storage capacity for PCs by the original factory, it is expected that the price of cSSD from the original factory will tentatively increase in the market situation where the original factory supply is limited and profits are maintained. Of course, this is highly anticipated by major PC customers and still requires a lot of bargaining. With the reduction of DRAM production capacity in the old process, the supply of consumer PC DDDR4 is extremely tight. The contract price of PC DDR4 is expected to increase significantly by 30% to 40%, and the price of PC DDR5 is expected to remain stable at a medium to low single digit percentage month on month growth. Server: Starting from 2024, the demand for DRAM bits in servers will surpass that of Mobile DRAM, making servers the largest application market for DRAM. In 2025, the demand for DRAM bits in servers and HBM will continue to maintain strong growth momentum. The proportion of server DRAM bit demand is expected to further expand to 36%, and the proportion of HBM bit demand is expected to reach 9%. HBM revenue is expected to account for more than 25% of the global DRAM market. Therefore, in order to comply with the trend of upgrading the demand for AI server DRAM, DRAM manufacturers are competing to make efforts in server DDR5 and HBM, significantly reducing unprofitable old DRAM processes such as 1x/1ynm, and actively expanding advanced DRAM processes such as 1a/1bnm. However, DDR4 and LPDDR4X are basically stuck in the old process. With the rebound in stocking demand, the market has exposed a certain supply gap, and spot prices have risen sharply compared to contract prices. To ensure the stability of the supply chain, the shortage of DDR4/LPDDR4X will accelerate the migration of terminal demand to DDR5/LPDDR5X. With the increasing shipment volume of HBM3e equipped on the new generation AI server Blackwell, HBM has a significant impact on the global DRAM supply and market landscape. In the first quarter of 2025, SK Hynix's DRAM sales surpassed Samsung for the first time in history, ranking first in the DRAM market.   In the first quarter, SK Hynix, Samsung, and Micron had DRAM market shares of 36.7%, 35.6%, and 22.9%, respectively. At the same time, DRAM technology is accelerating its migration towards 1b, 1 γ, and more advanced processes. DRAM manufacturers are actively promoting the transition of LPDDR4X to LPDDR5X and DDR4 to DDR5 products, and seizing the market advantage of 12Hi HBM3e and HBM4. The global DRAM market is firmly moving towards high-performance, high-capacity, and high profit development. In order to improve operating profits and fully meet the memory performance and capacity requirements of AI servers, DRAM manufacturers are aggressively shifting towards advanced DRAM processes, significantly reducing the production capacity of the unprofitable 1y/1znm DRAM old process, and actively promoting the research and mass production of the sixth generation 10nm process DRAM. The prices of spot DDR4 and DDR5 chips have all risen, with some DDR4 chip prices doubling in the second quarter. According to CFM flash memory market data, since the second quarter, DDR5 16Gb eTT/16Gb Major/24Gb Major has increased by 11%, 7%, and 24% respectively, while DDR4 4Gb/8Gb eTT/8Gb 3200/16Gb eTT/16Gb 3200 has increased by 27%, 60%, 137%, 60%, and 167% respectively. Japanese company MGC recently notified carrier manufacturers that the delivery time for some BT materials (NS/NSF Low CTE Glass) with a thickness of only 0.04 or 0.06mm has reached 16 to 20 weeks, which is more than twice the normal period in the past. The shortage of key materials such as packaging substrates continues to ferment and propagate to the finished product end, making it even more difficult to produce LPDDR4X products that are already affected by the shortage of storage resources. Especially, the delivery pressure of 1/2/3/4GB low capacity LPDDR4X is more prominent, driving the price of LPDDR4X products to continue to rise. The prices of related integrated eMCP and uMCP products have increased in line with the rise in LPDDR4X prices.

The 2025 Bluetooth Asia Conference has successfully concluded, showcasing a unique Bluetooth wireless world through its conference and forum. Neville Meijers, CEO of the Bluetooth Technology Alliance, mentioned in his keynote speech that "Bluetooth is not just a technology, but a global community with the common goal of meeting basic connectivity needs. The Bluetooth Alliance expects global Bluetooth device shipments to exceed 5.3 billion units by 2025 and reach nearly 8 billion units by 2029." The Bluetooth Asia Conference has three main highlights: 1 The combination of AI and Bluetooth technology is mainly aimed at audio and end-to-end computing; 2. The application of Auracast low-power Bluetooth audio in scenarios; The first and second points of Bluetooth channel sounding in automobiles and IoT are more about the combination of new applications and existing technologies, while the third point showcases a new Bluetooth wireless world - Bluetooth channel sounding. Bluetooth Channel Sounding is an important technology introduced in Bluetooth 6.0, aimed at improving positioning accuracy and suitable for scenarios such as automotive digital keys and asset tracking. For example, in the battle of digital car keys, Bluetooth channel detection, NFC, and UWB, Bluetooth channel detection, as a highlight of BLE 6.0, has improved positioning accuracy and become the mainstream choice for digital car keys. Bluetooth wireless technology has been rapidly advancing and its application areas are becoming increasingly diverse. In the development process of wireless technology, it is becoming a big brother from a little brother, which once again proves that choice is greater than effort. In 2024, domestic Bluetooth chip manufacturers will take off collectively and make a huge profit of 790 million yuan in a year. As one of the core innovations of Bluetooth 6.0, Bluetooth Channel Sounding technology will bring new business opportunities to Bluetooth wireless applications. Through phase ranging (PBR) and round-trip time (RTT) measurements, centimeter level accuracy positioning has been achieved, providing technical support for high-precision scenarios in the automotive and IoT fields. The following will be discussed from three aspects: technical characteristics, application scenarios, and practical cases. Firstly, the principle of Phase Based Ranging (PBR) utilizes 79 physical channels in the 2.4GHz frequency band to calculate distance through multi frequency signal phase differences, solving the accuracy limitations of traditional Bluetooth positioning technologies such as RSSI. Compared with traditional trilateration methods, anti-interference and security are enhanced through dynamic channel switching and bidirectional authentication mechanisms in channel detection, which enhances the ability to resist multipath interference while ensuring communication security. Compatibility optimization works in conjunction with existing Bluetooth protocols such as broadcast and AoA/AoD, enabling low-power deployment without the need for additional hardware, making it suitable for large-scale IoT devices. 2、 The application scenarios in the fields of automotive and IoT include intelligent automotive digital keys. The Star Flash car key equipped on the M9 is based on channel detection technology, which improves positioning accuracy by 5-6 times compared to traditional Bluetooth solutions and achieves centimeter level unlocking. Zhiji L6 supports on-site experience of Bluetooth channel detection technology through Yinji Technology's digital key solution. CEVA's Bluetooth channel detection IP solution for industrial and asset tracking meets the high-precision asset positioning needs in industrial environments, such as warehouse management and equipment tracking. Smart homes and smart cities have precise distance sensing capabilities through Bluetooth channel detection, which can optimize user experience in scenarios such as smart access control and indoor navigation, and reduce deployment costs. 3. Commercialization progress and challenges Standardization process: Bluetooth SIG completed technical specifications in 2024 and showcased derivative applications such as HDT (High Throughput Data Transmission) at the 2025 Bluetooth Asia Conference. Ecological Expansion: Channel detection complements technologies such as Star Flash and UWB, and may achieve multi technology integration solutions in areas such as connected vehicles and AR/VR in the future. Cost and power consumption: Although dedicated hardware is not required, multi-channel switching may increase chip design complexity, requiring a balance between accuracy and device endurance. Overall, Bluetooth channel detection technology is accelerating its transition from standardization to commercialization. Its high precision and low cost characteristics have opened up new application space for the automotive and IoT fields, but further optimization of multi device collaboration and energy consumption performance is also needed.

STMicroelectronics (ST), as a leading global semiconductor supplier, has attracted much attention for its layout in the Chinese market. Recently, the "2025 STM32 Summit of STMicroelectronics" was held in Shenzhen, where ST and domestic engineers and media elaborated on its technology, products, and strategic layout in depth. As the first overseas semiconductor giant to deeply implement the concept of "in China, for China", what are the unique features of ST's localized production in China? This article will delve into the progress of ST's highly anticipated "MCU dual supply chain" and "Chongqing SiC factory" in China.       MCU Dual Supply Chain: The "Chip" Dynamic Connection between ST and the Chinese Market At the end of 2024, in the context of increasing attention to supply chain security, ST announced the commission of Huahong to manufacture 40nm eNVM MCU products, achieving localization of STM32 products and providing customers with a seamless second source verification process. According to ARNAUD JULIENNE, Vice President of Digital Marketing at ST China, the production line will achieve mass production by 2025. Image: ARNAUD JULIENNE, Vice President of Digital Marketing at ST China ST has innovatively opened up the dual supply chain path of MCU in China, becoming a pioneer among international giants. This strategy will create a solid security barrier for MCU. Firstly, in terms of production technology, the cooperation between ST and Huahong is not simply a contract manufacturing relationship. But rather a 'full replication of process' practice - the production line uses the same mask, equipment, and process parameters as European factories to ensure zero performance difference between Chinese production lines and overseas products. Julian said that the cooperation between ST and Huahong began two or three years ago. ST had already arranged more than 100 factory experts to be stationed at Huahong Hongli two years ago, guiding them step by step to use the same equipment and production materials as ST factory, and strictly following ST's process specifications to produce ST's MCU. After long-term cooperation and communication, both parties have achieved sufficient guarantees for domestic customers in terms of production technology and supply strategies. Julian emphasized that "the quality of wafers produced in European factories is the same as that of wafers produced in Huahong Hongli." This consistency includes chip specifications, electrical characteristics, product quality, reliability and the same part number. In other words, the ST chips purchased by customers in the domestic production line they cooperate with Huahong have the same quality as other global production lines. Secondly, in terms of product supply, ST's dual supply chain value is not only in providing customers with products from Chinese origin, but also in providing customers with a more flexible global supply chain system. Julian further elaborated on the strategic idea of "dual supply chain", stating that ST has production capacity in different countries such as China, France, and South Korea. Some customers are very concerned about the wafer origin, and for these customers, ST will prioritize providing wafers from the required origin. For customers who do not have such requirements, ST will unify the global supply chain to meet customer needs. This means that while ensuring that the quality of STM32 produced domestically is no different from products from other global origins, the domestic production line is a major extension of ST's global supply chain, which can better ensure that ST meets the needs of customers both domestically and internationally. For example, if the customer wants to export in the future, ST has STM32 produced on foreign production lines; If customers want to avoid some import issues, ST has domestically produced STM32. This is the greatest value for customers of ST's "in China, for China" strategy, and it is also a supply chain advantage that other overseas chip manufacturers currently do not possess. Julian also gave a candid response regarding the cost issue of domestic MCUs. Julian stated that reducing the localization cost of STM32 is not ST's top priority. ST's top priority is to prepare two sets of supply chains with consistent quality for Chinese customers in the current geopolitical uncertainty.     Silicon carbide 'Chongqing fortress': ST ambition under rare earth strategy In addition to MCU, the progress of the Chongqing 8-inch SiC factory jointly built by ST and Sanan Optoelectronics has also attracted attention. This is another masterpiece of ST China's production line. This is not only the world's first joint venture project to mass produce silicon carbide devices in China, but also a key milestone for ST's layout in the field of silicon carbide in China. On February 27th of this year, Sanan Optoelectronics and STMicroelectronics announced the official launch of the silicon carbide wafer fab jointly established by Sanan Optoelectronics and STMicroelectronics in Chongqing (Sanan Optoelectronics holds 51% of the shares and STMicroelectronics (China) Investment Co., Ltd. holds 49% of the shares). It is reported that this will become the first large-scale production line for 8-inch automotive grade silicon carbide power chips in China. After the project is fully operational, it can produce about 10000 automotive grade wafers per week. Julian stated that the project will achieve mass production in the fourth quarter of this year. Similar to the Huahong project, ST has built a complete high-quality IDM localization chain in the field of silicon carbide. From substrate to wafer, and then to packaging, every link is closely interconnected: Sanan Optoelectronics' substrate factory provides high-quality raw material guarantee for this cooperative project, while in the wafer manufacturing process, ST strictly controls the production parameters to ensure the excellent performance of the wafers. The optimized design of the packaging process further enhances the reliability and integration of the product. Through this complete chain, ST has achieved full process autonomy and controllability from raw materials to finished products, greatly improving the delivery speed and quality of products. Due to considerations of supply chain security and cost optimization, international giants have accelerated the localization of SiC materials. ST's Chongqing project not only helps ST avoid potential risks brought by domestic rare earth export controls, but also greatly reduces SiC costs with the support of Sanan Optoelectronics' substrate factory, injecting strong momentum into ST's SiC devices in market competition. The ST project once again leads the industry and provides a successful example for the industry. It is worth noting that with the gradual release of domestic production capacity by international giants such as ST, the supply of SiC market will continue to increase, and a price war may be imminent. For domestic manufacturers, this is both a challenging test and a rare opportunity. Under the pressure of price wars, domestic manufacturers will have to accelerate the pace of technological research and development, improve product performance and quality, in order to stand out in the fierce market competition. At the same time, the decrease in prices will further expand the application scope of silicon carbide, providing a broader market space for domestic manufacturers and promoting their technological upgrading and industrial growth.    

  ST: Establishing joint venture wafer fabs in China+collaborating with Chinese wafer foundries ST's SiC wafers and STM32 MCUs both adopt a dual supply chain strategy. For SiC wafers, ST is laying out production capacity through joint ventures with local enterprises. ST and Sanan Optoelectronics have jointly established Anyifa Semiconductor in Chongqing, China. The joint venture factory plans to have an annual production capacity of 480000 8-inch silicon carbide wafers, mainly producing automotive grade electronic control chips. The joint venture factory adopts ST's SiC patented manufacturing process technology and selects locally produced SiC substrates in China. The packaging and testing of SiC devices are completed by STMicroelectronics Shenzhen Saiyifa, forming a complete localized 8-inch SiC supply chain in China. For STM32 MCU, ST has chosen to cooperate with local wafer foundries. In November 2024, ST announced that it had commissioned Huahong to manufacture STM32 MCUs and other products with 40nm nodes in China to achieve localization of STM32. On this basis, ST's STM32 MCU can provide fully localized supply chain support for global OEM manufacturers operating in China, as well as supply chain options for Chinese OEM manufacturers operating internationally. For gallium nitride (GaN) business. ST announced in March 2025 that it had signed a GaN technology development and manufacturing agreement with 8-inch silicon-based GaN manufacturer Innolux to collaborate on a joint development plan for GaN power technology. Based on a flexible supply chain layout, both parties will expand their respective GaN product portfolios and market supply capabilities, effectively enhancing supply chain resilience. ·NXP: Establishing a joint venture wafer fab in Singapore to expand its supply chain in China NXP is also actively promoting the strategy of "in China, for China". On the one hand, NXP has established a joint venture, VSMC, with world leading companies in Singapore, a tariff friendly region of China; On the other hand, NXP announced in December 2024 that it plans to build a new supply chain in China and bring front-end manufacturing to China's domestic market. The total investment of the VSMC project is approximately 7.8 billion US dollars (60% owned by World Advanced and 40% owned by NXP). VSMC's first 12 inch wafer fab uses 130nm to 40nm technology to produce mixed signal, power management, and analog products, supporting the needs of end markets such as automotive, industrial, consumer electronics, and mobile devices. Last December, Andy Micallef, Executive Vice President of NXP, announced that the company was seeking to expand its supply chain in China to provide services to enterprises that require domestic supply chains in China. NXP stated at the time that it would relocate some of its chip front-end manufacturing to China and was exploring the possibility of establishing cooperation with local wafer foundries. ·Infineon: localizing production of commodity level products in China At the end of last year, Infineon CEO Jochen Hanebeck stated that the company is localizing the production of commodity grade products in China, with the aim of strengthening close ties with customers in the Chinese market. On June 11, 2025, Infineon officially released its localization strategy of "in China, for China". In terms of localized production, Infineon's automotive business has already completed localized mass production of multiple products. The company plans to cover the localization of major products by 2027, including microcontrollers, high and low voltage power devices, analog mixed signals, sensors, and storage devices. In order to better serve the Chinese automotive market and meet the increasing demand for MCUs from Chinese customers, the next generation 28nm TC4x product will be produced locally in China for both front-end and back-end production. ·US semiconductor IDM is also flexibly responding to tariff challenges During the earnings conference call for the first quarter of 2025, Haviv Ilian, CEO of Texas Instruments, stated that the world is currently in a highly uncertain period, with tariffs and geopolitical factors disrupting the global supply chain and causing unpredictable economic conditions; China is not only an important terminal market, but also a key node in the global supply chain. He also emphasized that the company has established a highly flexible supply chain system that can optimize production paths and reduce the impact of tariffs on costs. At present, TI adopts the "dual design" of its internal manufacturing process. For example, part of its embedded processors are produced by Taiwan, China's OEM factory, and the other part is produced by Lee Hai's factory in the United States. In the case of high tariffs between China and the United States, the products delivered by TI to Chinese customers are produced by Taiwan, China OEM. Global layout, process technology, and production capacity distribution of semiconductor IDM The article "Global Layout and Capacity Inventory of Semiconductor Wafers (Part 1)" introduces Foundry's global layout and capacity distribution, with a focus on the global layout and distribution of semiconductor IDMs. The previous article introduced Samsung's situation, so this article will not elaborate further. ·Intel   1.1: Distribution of Intel's global manufacturing bases Image source: Intel official website Intel proposed the "IDM 2.0" strategy in 2021, investing billions of dollars to lay out wafer fabs, attempting to regain the voice of chip manufacturing through a three pronged approach of "self construction+foundry+cooperation". In June 2023, Intel announced at an investor webinar that it had combined its Technology Development (TD), Contract Manufacturing, and IFS departments and required the department to be responsible for its own profits and losses. According to the plan, Intel's foundry business unit (IFS) will achieve breakeven by the end of 2030.   1.2: Intel's global wafer fab layout and process technology. As of late June 2025, Intel operates over 10 wafer fabs in 7 cities worldwide, mainly located in Arizona, Oregon, New Mexico, Ohio in the United States (awaiting mass production), Lexlip in Ireland, Jerusalem in Israel, and Saxony Anhalt in Germany (awaiting mass production); We operate testing plants in six cities worldwide, including Penang and Kulin in Malaysia, Chengdu in China, San Jose in Costa Rica, Ho Chi Minh City in Vietnam, New Mexico in the United States, and Wroc ł aw in Poland (awaiting mass production). ·Texas Instruments   2.1: Layout of Texas Instruments' global wafer fabs and packaging and testing facilities. Source: In recent years, Texas Instruments (TI) has continued to increase its investment in 12 inch (300mm) processes from 45nm to 130nm. The company has invested in the construction of seven new 12 inch (300mm) wafer fabs, which will bring improvements in scale, efficiency, and quality. TI is building a new 12 inch semiconductor wafer manufacturing plant (SM1, SM2, SM3, SM4) in Sherman, Texas, with a total investment of $30 billion. After completion, the plant will produce millions of analog and embedded processing chips per day. Among them, SM1 will be put into operation as early as 2025.   2.2: Texas Instruments Global Wafer Plant Layout and Process Technology In addition to wafer fabs, TI also owns and operates assembly and testing facilities worldwide, achieving regional diversification and controlling the supply chain on this basis. Currently, TI is investing in enhancing its assembly and testing capabilities, and improving the availability of manufacturing processes in multiple locations. TI has closed survey bases in Aguascalientes in Mexico, Kuala Lumpur and Malacca in Malaysia, New Taipei City in Taiwan, China, Baguio City in the Philippines, Clark Free Port District and other cities. It is expected that by 2030, over 95% of the company's wafer manufacturing, assembly, and testing operations will be transferred internally. ·SK Hynix   3.1: SK Hynix has production and manufacturing bases in four cities around the world. Image source: SK Hynix official website SK Hynix was formerly known as Modern Electronics Industry Co., Ltd., established in 1983. After being acquired by SK Group in 2012, it was officially renamed SK Hynix Co., Ltd. SK Hynix is committed to producing semiconductor products primarily consisting of DRAM, NAND Flash, and CIS non memory. Currently, the company has four production bases in Lichuan and Cheongju, South Korea, Wuxi and Chongqing (closed testing factory), China, and sales, research and development bases in 16 countries and regions worldwide.   3.2: SK Hynix Global Wafer Plant Layout and Capacity In recent years, SK Hynix has increased its business profits by building new production lines, renovating production lines, and relocating factories. In terms of new production lines, SK Hynix plans to build four 12 inch wafer fabs in Longin City, Gyeonggi Province, South Korea, forming the Longin Semiconductor Cluster (Phase 1/2/3/4). Phase 1 is scheduled to be completed in May 2027 and will also build a "mini wafer fab" equipped with 300mm wafer processing equipment, providing a research environment for Korean component, material, and equipment suppliers to develop, showcase, and evaluate new technologies. In terms of production line renovation, by the end of February 2025, SK Hynix will complete the renovation of its M10F factory in Licheon City, Gyeonggi Province, South Korea, and transform it into a production base for packaging HBM. The M10F factory adds HBM packaging capacity for 10000 wafers per month, increasing the total production capacity from 120000 wafers to 130000 wafers. It is expected that by the end of 2025, with the commissioning of the M15X factory in Qingzhou City, the total production capacity will reach 160000 to 170000 wafers. In terms of factory relocation, SK Hynix System IC (formerly known as SK Hynix Foundry Business Unit) will relocate its M8 factory located in Cheongju, South Korea to Wuxi, China and rename it for registration before May 2022. M8 factory has a monthly production capacity of 100000 8-inch wafers, producing DDI, PMIC, and CIS. Original M8 factory produces DDI for LG LCD screens, PMIC for Silicon Mitus, and CIS for SK Hynix. SK Hynix also has a packaging and testing factory in Chongqing, China - Aisikai Hynix Semiconductor (Chongqing) Co., Ltd., which mainly produces Nand Flash, a flash memory product suitable for mobile terminals. The product is mainly used in mobile terminal devices such as smartphones, tablets, USB, etc. ·Meiguang   4.1: Micron's global wafer fab layout and production capacity. Micron's headquarters is located in Boise, Idaho, and its wafer fabs are spread across Boise, Idaho in the United States, Taichung in Taiwan, Hiroshima in Japan, and Singapore. According to the news released by Micron in mid June 2025, the company plans to invest $200 billion to support semiconductor manufacturing and research and development in the United States, introducing HBM manufacturing to the domestic market. It is reported that Micron will start building the Boise wafer fab in October 2023 and begin producing DRAM in 2027. Now, the company plans to build a second wafer fab in Boise, expected to be completed and put into operation before the first wafer fab in New York State, and to create synergies with existing production lines. After the completion of the two factories, the HBM packaging project will be launched. Over the past few decades, Micron has also expanded its business through continuous mergers and acquisitions. In 2010, the company acquired Numonyx, a flash chip manufacturer, for $1.27 billion; In 2013, Micron acquired Elpida Memory and expanded its memory business; In 2016, Micron also acquired PC memory manufacturers Rexchip and Innotera Memories; In 2024, Micron acquired AU's wafer fabs in Taichung and Tainan to support its DRAM production business in Taichung and Taoyuan factories. The Hiroshima plant in Japan is a facility that was acquired after the merger with Erbida. By 2025, the Hiroshima plant will produce 1 gamma DRAM, and in addition, it will also produce HBM. According to the plan, Micron will also build a new DRAM chip manufacturing plant in Hiroshima and introduce EUV equipment, with advanced DRAM being mass-produced as early as the end of 2027; Micron Taichung Plant 4 was acquired from AU Optronics, and together with A3 Plant, it forms Micron's vertically integrated DRAM manufacturing base in Taiwan. Based on this, Micron Taichung Plant will increase its monthly wafer production to 60000 pieces by the end of 2025. ·STMicroelectronics   4.2: ST's front-end/back-end factory layout supports global enterprises' multi wafer procurement strategy (information updated as of March 2025) Image source: ST STMicroelectronics' wafer manufacturing plants are mainly concentrated in Europe and Asia, specifically distributed in Norrkoping, Sweden, Crolles, Rousset, Tours in France, Agrate and Catania in Italy, Chongqing, Singapore and other regions in China. In addition, ST also has semiconductor sealing and testing plants in cities such as Rennes in France, Marcianise in Italy, Bouskoura in Morocco, Kirkop in Malta, Shenzhen in China, Muar in Malaysia, and Calamba in the Philippines.   5.1: STMicroelectronics' global wafer fab layout and production capacity. Based on the layout of the front/back processes mentioned above, ST can support global enterprises' multi wafer procurement strategies. For customers who are very concerned about the origin of wafers, ST will prioritize providing wafers from the required origin for these customers; For some customers who are not sensitive to their origin, ST will coordinate the entire global supply chain. Now, ST is actively promoting the upgrade plan of its SiC wafer fab, with the core goal of gradually upgrading the original 6-inch production line to an 8-inch production line starting from Q3 2025. For example, its Catania factory in Italy will transition from 6-inch to 8-inch production processes in Q3 2025; Subsequently, the Singapore factory will also initiate an upgrade to 8-inch SiC wafer production within 2025. This move aims to consolidate its leading position in the rapidly growing high-performance power semiconductor market by improving production efficiency and reducing costs, and to coordinate with its dual supply chain system construction strategy. ·NXP NXP currently has 8 wafer fabs (including 4 planned to close 8-inch fabs). Due to the high cost and outdated technology of 8-inch fabs (all of which are mature processes above 100nm), the company is gradually phasing out 8-inch fabs and shifting towards 12 inch fabs. Among the four 8-inch wafer fabs that NXP will close, one is located in Nijmegen, the Netherlands, and three are located in the United States. After the closure, production capacity will be relocated to the 12 inch production lines of the VSMC and ESMC joint ventures.   5.2: NXP's global wafer fab layout (excluding the planned closure of 4 8-inch wafer fabs) In the future, NXP may reduce to 5 core fabs. In addition, NXP has invested $7.8 billion in its joint venture plant in Singapore (VSMC, planned for mass production in 2027), focusing on 130nm-40nm mixed signal and power management chips, with a monthly production capacity of 55000 wafers by 2029; NXP also has a joint venture wafer fab ESMC in Germany, but it only holds a 10% stake and is operated by TSMC (which holds a 70% stake). The total investment of the fab exceeds 10 billion euros, with a planned monthly production capacity of 40000 12 inch wafers. Construction will begin in the second half of 2024 and production will begin at the end of 2027. ·Infineon   6: Distribution of Infineon's 15 factories (including front-end and back-end factories, data as of September 30, 2024) Image source: Infineon has a total of 15 factories worldwide (including front-end and back-end factories) as of September 30, 2024. Among them, the United States has gathered several production bases of Infineon, with wafer fabs located in Austin, Texas and Mesa, Arizona. At the end of February 2025, the company announced the sale of its 8-inch wafer fab Fab25 located in Austin, Texas, to SkyWater. It is reported that Fab25 focuses on producing 130nm to 65nm basic chips that are crucial for industrial, automotive, and defense applications.   7: Infineon's global wafer fab layout (incomplete statistics). Infineon also has front-end wafer fabs in Kulin Malaysia, Regensburg and Dresden in Germany, and Filach in Austria. Among them, the K3 wafer fab in Kulin, Malaysia is an 8-inch SiC wafer fab. Phase 1 has been put into operation since August 2024, with initial production capacity focused on SiC power semiconductors. It is expected that after Phase 2 is put into operation, the total production capacity will increase to the world's largest scale, covering the production of gallium nitride epitaxy; The Smart Power Fab in Dresden, Germany is the world's first semiconductor factory to comply with Industry 4.0 standards, covering wafer processing, testing, and separation processes; It is planned to start production in 2026 and is expected to reach full capacity production by 2031. ·Ansenmei Figure 6: Anson's manufacturing factories are scattered in 9 countries around the world. Image source: Anson has 19 production factories (including front-end and back-end processes) in 9 countries, located in the United States, Canada, China, Czech Republic, Japan, Malaysia, Philippines, South Korea, and Vietnam. Anson Semiconductor was originally part of Motorola's semiconductor division, spun off from Motorola in 1989, and went public on NASDAQ in 2000. The 6-inch wafer fab in Roznov, Czech Republic, the 6-inch wafer fab/packaging and testing plant in Seremban, Negeri Sembilan, Malaysia, and the packaging and testing plant in Kamona, Krabi Province, Philippines, which are still in operation, are all factories that were spun off from Motorola at that time.   8: Anson's global manufacturing base layout (including wafer fabs and packaging and testing facilities). In addition, most of the wafer fabs/packaging and testing facilities currently operated by Anson are acquired through mergers and acquisitions. Including its 12 inch wafer fab located in East Fishkill, New York, which was acquired in 2019 through the purchase of the Grosvenor Fab10 wafer fab, and its 8-inch wafer fab located in South Par, Iowa, which was acquired in 2014 through the purchase of Aptina Imaging. In addition, its 8-inch wafer fabs located in Gresham, Oregon, Mentintop, Pennsylvania, Shenzhen, Guangdong, China, and Wakamatsu, Japan, as well as its 8-inch/6-inch wafer fabs in Bucheon, Gyeonggi Province, South Korea, and its packaging and testing plants in Tongna, Vietnam, Tarak, Philippines, and Burlington, Ontario, Canada, all came from mergers and acquisitions.  ·ADI Figure 7: ADI Global Manufacturing Base and Supply Chain Network Image Source: ADI's product supply chain is mainly completed through the collaboration of "independent wafer fabs+external foundries". The company has deployed 10 independent factories (including front-end and back-end factories) and 50 supply chain factories worldwide, covering 15 countries or regions. The front-end wafer fabs within ADI lead mature processes (Beaverton, Oregon/Limerick, Ireland, USA), and their advanced process technologies are mainly provided by their foundry partners.   9: ADI's internal manufacturing base layout (including wafer fabs and packaging and testing plants) Overall, ADI's internal factories contribute about 50% of wafer production capacity, 80% of testing capacity, and 20% of packaging capacity. Currently, ADI is expanding its wafer fab capacity through internal investment. It is expected that by the end of 2025, the production capacity of wafer fabs located in the United States and Europe will double - the Beaverton factory in Oregon is renovating an 8-inch wafer fab, increasing its cleanroom area by 25000 square feet and doubling its production capacity; The production area of the Limerick factory in Ireland will be expanded by 15000 square feet, with a threefold increase in production capacity; The Camus factory in Washington state is also expanding its production capacity. Most of the testing work for ADI products is conducted in factories in the Philippines, Malaysia, and Thailand, and the assembly business is outsourced to trusted partners. ADI is expanding its testing facilities in Malaysia and Thailand, and has also expanded its campus in the Philippines. In addition, ADI is cross validating testing processes with external partners to ensure that dual procurement can be conducted when needed. ·Microchip Technology Microchip's hybrid supply chain strategy combines US wafer manufacturing plants with global assembly facilities, fully utilizing internal and external foundries and OSAT manufacturers. With the support of strategic partnerships, this manufacturing ecosystem can optimize the production of high-value markets while balancing cost-effectiveness and reliability. In May 2025, Microchip closed its Fab2 wafer fab in Tempe, Arizona, which has a monthly production capacity of 20000 8-inch wafers (1 μ m-250nm process). Its technology and products will be transferred to Fab4 and Fab5 factories. At the same time, Fab4 and Fab5 factories have laid off employees, and the production capacity of the two wafer fabs has been reduced to below short-term demand levels. After the excess inventory is digested, it will gradually return to demand matching production capacity. Fab4 will still maintain a two-week preparation time for resuming production after the layoffs.   10: Global wafer fab layout and current situation of Microchip Technology. In addition, the company's packaging and testing bases are distributed in the United States (Beverly, Massachusetts; Lawrence and Lowell, Massachusetts; Holly Springs, Pennsylvania; San Jose and Garden Grove, California; Simsbury, Connecticut), France, the United Kingdom, Ireland, Germany, Thailand, the Philippines, and other places.

On June 22, American chip manufacturer Wolfspeed announced that it would file for bankruptcy under a restructuring agreement that would eliminate billions of dollars in debt and give creditors control of the company. Wolfspeed stated that the restructuring plan has received sufficient support from creditors, including semiconductor manufacturer Renesas Electronics and investment firm Apollo Global Management. Wolfspeed stated that it will continue to seek approval from more creditors before filing for bankruptcy under bankruptcy laws. Robert Feurle, CEO of Wolfspeed, stated in a statement: "After evaluating potential options for strengthening our balance sheet and adjusting our capital structure, we have decided to take this strategic move because we believe it will put Wolfspeed in the best position in the future. ”According to its proposal, creditors' debts will be converted into equity, and existing shareholders will receive at least 3% and up to 5% of new shares. These ratios imply higher shareholder losses, but higher than the typical level of most bankruptcy cases. The company hopes to continue trading on the New York Stock Exchange, but acknowledges in a statement that it may delist "for a period of time," and Wolfspeed promises that this process will not affect its commitments to customers and suppliers. Wolfspeed expects to emerge from bankruptcy by the end of September after cutting 70% of its debt (approximately $4.6 billion). At that time, the new shareholders will appoint new members of the board of directors. As of the end of March, Wolfspeed held $1.3 billion in cash, which is a significant amount for a company preparing to apply for bankruptcy protection under bankruptcy law. However, the company will face over $6 billion in debt in the coming years, including payments due in 2026, 2028, 2029, 2030, and 2033. The company has rejected the proposal to restructure next year's debt and instead insists on what Wolfspeed's head of investor relations, Tyler Gronbach, previously called a 'comprehensive solution'. According to its bankruptcy proposal, these debts will be reduced, merged, and postponed - with an earliest maturity date of 2030.

The news of mergers and acquisitions by semiconductor distributors has once again come. Kaga Electronics announced that it will acquire the common stock of Xierong Industries through a public offering of shares (TOB) in May 2025. The TOB acquisition period starts on June 2nd and ends on July 11th. We plan to acquire approximately 2.2 million shares, with a total expected acquisition amount of up to approximately 8.7 billion yen. Kaga Electronics was founded in Tokyo on September 12, 1968. It is a well-known independent comprehensive electronics trading company in Japan and a listed company in the Tokyo Stock Exchange. It focuses on the manufacturing of electronic components, semiconductors, EMS, and information equipment. Proxy brands include Mitsubishi Electric, Renesas, ADI, Omnivision, etc. Kaga Electronics had sales of 547.779 billion yen and operating profit of 23.61 billion yen in the fiscal year of March 2025, making it one of the top five major semiconductor/electronic product distributors in Japan. On the other hand, the sales revenue of Xierong Industry in the fiscal year of March 2025 was 57.79 billion yen, with an operating profit of 974 million yen. After the merger, it will become a distributor with sales exceeding 600 billion yen, but it has not yet reached the scale of 1-341 trillion yen of Macnica Holdings, the current leading electronic distributor in Japan, in the fiscal year of March 2025. At present, the electronic distribution pattern in Japan is dominated by Macnica Holdings, the only company with sales exceeding 1 trillion yen, ranking first. The second tier consists of several companies with sales between 400 billion and 500 billion yen, followed by distributors with sales of 200 billion yen and 100 billion yen. In recent years, the trend of integration between distributors with larger sales scales, or large distributors acquiring small distributors, has been accelerating. About a year ago, Ryoyo Electro (with sales of 129.9 billion yen as of January 2023) merged with Ryosan (with sales of 325.6 billion yen as of March 2023) to form Ryosan Ryoyo Holdings (HD). The background is that with the acceleration of the Internet of Things (IoT) and digital transformation (DX), the rapid use of new technologies has brought significant environmental changes to the industry, and the functions and roles required for electronic distributors are changing, including the impact of intensified competition between companies and geopolitical risks related to mergers and acquisitions with semiconductor manufacturers and other manufacturers. The merger of the two companies will bring good synergies. Ryosan has many customers in the automotive field, while Ryoyo Electro has many customers in the medical field, which is conducive to integrating and expanding the customer base of the two companies. On May 14th of this year, Ryosan Ryoyo Holdings (HD) announced its first annual financial report after the merger, with sales of 359.811 billion yen and operating profit of 8.542 billion yen. The overall group goal set by the company is to achieve sales of 500 billion yen and operating profit of 30 billion yen for the fiscal year ending March 2029. In addition, although the types are slightly different, Kanematsu also acquired Electronics End Materials Corporation, a distributor of semiconductor silicon wafers, in March 2025. Over time, the restructuring of Japanese semiconductor distributors is not a new phenomenon: in 2003, Macnica and Fuji Electronics merged to form Macnica Fuji Electronics HD. In 2007, UKC HD and Vitec HD merged to form Leicester HD. The large number of small and medium-sized enterprises is a prominent feature of Japan's semiconductor distributor industry. Traditionally, there have also been many distributors affiliated with the manufacturer system, which has given rise to unique business practices. Therefore, even if there are significant changes in the external environment, it is often difficult to break the existing inertia, and some distributors are forced to struggle. This situation was particularly evident during the COVID-19 epidemic. Despite the tight global semiconductor supply, there is still a market with smooth circulation, which exposes the weakening purchasing power of Japanese distributors, posing a huge challenge to them. Against the backdrop of rising semiconductor/component prices, rising logistics costs, and foreign distributors entering the Japanese market and strengthening their business layout in Japan, it has become increasingly difficult for a single distributor to continue investing. In order to effectively compete with global suppliers, avoid the situation of "not being able to buy others" and maintain this ability, the integration and restructuring trend of Japanese electronic distributors will continue to be promoted in the future. In 2019, five years ago, Texas Instruments (TI) announced the termination of its exclusive distribution agreements with its sales partners, including Marubeni, Avnet, and WPG. This news caused a huge shock in the distributor industry. In addition, mergers and acquisitions by chip manufacturers may also be an important reason for the restructuring of Japanese chip distribution companies. Renesas Electronics acquired Intersil Corporation in 2005 and IDT Corporation in 2007. Since 2008, there has been a trend of termination of distribution agreements between Renesas Electronics and semiconductor trading companies, such as the termination of distribution agreements with RYODEN Corporation (formerly known as Ryoden Shoji Corporation) at the end of February 2011. The role of Japanese distributors in the entire industrial chain is being questioned and reviewed again after the transformation of semiconductor supplier sales strategy and the structural change of the supply chain brought about by the COVID-19 epidemic.

Due to original manufacturers such as Samsung and Micron locking in the DDR5 and HBM markets, they will gradually stop supplying DDR4, which has led to a surge in DRAM stocking, especially with a significant increase in DDR4 prices. Micron officially confirmed that DDR4 will be discontinued. Last week, Micron confirmed that it has sent a letter to customers notifying them that DDR4 will be discontinued (EOL, End of Life), and it is expected to gradually stop shipping in the next 2-3 quarters. Sumit Sadana, Executive Vice President and Chief Commercial Officer of Micron, stated that DDR4 will continue to be severely out of stock. Sadana stated that the notice of discontinuation of DDR4/LPDDR4 has been handed over to customers recently, mainly targeting the PC and data center fields. It is expected that in the next three quarters, DDR4 DRAM for consumer, PC, and data center use will undergo production reduction or decrease. Future Micron DDR4/LPDDR4 DRAM is mainly provided to long-term cooperative customers in the automotive, industrial, and network industries. In February this year, it was reported that Micron, Samsung, and SK Hynix may stop producing DDR3 and DDR4 memory by the end of this year. In April, it was reported that Samsung notified PC manufacturers that DDR4 would be discontinued by the end of this year, with the final order date set for June. After the news of frequent price increases and factory shutdowns of storage products spread, it triggered a chain reaction in the DRAM market, leading to a surge in inventory. According to a report by Jibang Consulting, after the original factory announced EOL (termination of production), buyers rushed to replenish inventory, causing tight supply in the pellet spot market from April to May and a significant increase in prices. In June, the trend of storage product price increases has not stopped. According to the sales manager of a leading storage module manufacturer in Shenzhen, some DRAM products have recently experienced price increases, mainly DDR4 and DDR3. Some have risen by 100% during this period, while others have risen by 50% within a month. This month's increase is very significant. ”The supply of goods in the spot market is also scarce. According to the Science and Technology Innovation Board Daily, reporters inquired with multiple stores in Huaqiang North about a DDR4 3600MHz 16GB bare strip as the entry point, and the general feedback was "out of stock", indicating that this specification has experienced a shortage of stock on the channel end. Continuously inquiring about memory modules with multiple frequency and capacity specifications, the response received was almost always' out of stock '. Multiple Huaqiangbei merchants have provided feedback that DDR4 prices have recently increased significantly and are accompanied by a shortage of spot goods, while DDR5 prices are relatively stable. SSDs have already experienced a slight increase in prices and are currently stable. The flash memory market also shows that DDR4 memory modules have the strongest upward trend, with some products experiencing a cumulative price increase of over 30% in just two weeks. The price of low capacity eMMC has not only doubled compared to the end of last year, but 16GB/32GB/64GB eMMC has basically the same price. With the decreasing supply of MLC NAND, it will accelerate the further upgrading of storage capacity for application terminals such as TV/security/POS machines in the future. The flash memory market is expected to continue the price increase trend of DDR4 and DDR5 servers in Q3, but the increase will narrow and may fall within the range of 10% -15%. The expected price of DDR5 server products in the third quarter is expected to increase slightly compared to the second quarter, while in the fourth quarter, with the ramp up of original DDR5 production capacity and the improvement of yield, the supply side will concentrate on releasing production capacity, and server DDR5 products will face price fluctuations.

In the semiconductor world, some companies rely on technology to make a living, while others rely on patents to make a living. Qualcomm, on the basis of possessing these two, has built a chip empire through targeted "buying and buying". Today, Qualcomm is a chip giant spanning mobile phones, automobiles, the Internet of Things, and AI edge computing. But you may not know that the foundation of this empire is the technology teams and assets that have been quietly swallowed, polished with time and patience. GPU: Adreno Rising from the Afterglow of ATI The graphics processing capability of mobile devices in 2006 can be considered "primitive". At that time, the concept of smartphones had not yet become popular, with BlackBerry and Palm Pilot still dominating the market, and the release of the iPhone had to wait until 2007. In this era of mobile graphics processing where 'running a snake is enough', the vast majority of device manufacturers have extremely limited demand for GPUs, focusing more on basic 2D interface rendering and simple multimedia playback functions. However, it is during this seemingly calm period that a far-reaching technology acquisition is brewing. AMD has decided to acquire ATI Technologies for a sky high price of $5.4 billion in order to gain a graphics processing advantage in competition with Intel. This transaction not only changed the landscape of the PC graphics card market, but also unexpectedly planted an important seed for the mobile graphics processing field. In the AMD-ATI acquisition, AMD's main target was ATI's desktop and server GPU business, while ATI's mobile graphics division was considered a "peripheral" at the time. Although this department has considerable technical strength, the market prospects were not clear at the time. The graphics demand for mobile devices is limited, and the entire industry generally lacks confidence in the development potential of mobile GPUs. However, Qualcomm has demonstrated a forward-looking strategic vision. This company, which started with communication chips, is keenly aware that with the continuous enrichment of mobile device functions, graphics processing capabilities will become one of the core competitiveness of future mobile platforms. When AMD sold ATI's mobile GPU division as a "bundle", Qualcomm was quick witted and quickly acquired this experienced team at a relatively low price. After the acquisition, Qualcomm gave this newly acquired GPU division a memorable name: Adreno. This name is not randomly chosen, but rather a letter rearrangement and combination of ATI's famous GPU brand "Radeon". This naming convention not only reflects respect for ATI's technological heritage, but also symbolizes the team's fresh start under its new owner. The name Adreno itself carries a profound technical background. The Radeon series GPU once competed with NVIDIA's GeForce series in the PC field, with a deep accumulation of graphics processing technology. By preserving the symbolic expression of this technological DNA, Qualcomm is actually declaring to the market that Adreno will continue ATI's technological advantages in the field of graphics processing and further develop them. The original team from ATI has brought valuable technological assets to Adreno. These engineers not only have extensive experience in GPU architecture design, but more importantly, they have a deep understanding of various aspects of the graphics rendering pipeline, from vertex processing to pixel shading, from texture mapping to anti aliasing techniques. With the advent of the smartphone era, Adreno has ushered in its own shining moment. Qualcomm has deeply integrated Adreno into the Snapdragon system on chip platform, forming a collaborative optimization of components such as CPU, GPU, DSP, and modem. This SoC design concept not only improves overall performance, but more importantly achieves better power control and thermal management. The development history of Adreno series GPUs can be seen as a microcosm of the progress in mobile graphics processing technology. From the early Adreno 200 series to the current Adreno 740 series, each generation of products has achieved significant improvements in performance, power consumption, and feature support. Especially in terms of support for graphics APIs such as OpenGL ES, Vulkan, DirectX, Adreno has always maintained an industry-leading level. Today, Adreno has far exceeded the technological scope of ATI's mobile GPU. Modern Adreno GPUs not only support traditional 3D graphics rendering, but also integrate cutting-edge technologies such as machine learning acceleration, computational shaders, and variable rate shading (VRS). Adreno has demonstrated strong adaptability and scalability in emerging fields such as AR/VR applications, computational photography, and AI image processing. From a small team in the ATI laboratory to the graphics processing engine that supports billions of mobile devices worldwide today, Adreno's story can be considered a legend in the history of technology. The spark left by ATI, under the careful cultivation of Qualcomm, ultimately ignited the entire sky of mobile graphics processing. CPU: The confidence to invest in self-developed cores In the world of chip design, there is an unwritten rule: when giants start to feel threatened, real change is about to begin. In 2020, when Apple released the MacBook with the M1 chip, the entire industry was shocked. This is not only because M1's performance is stunning, but more importantly, it has proven a truth to the world: based on mobile chips, it is entirely possible to create products that can rival or even surpass traditional x86 processors. In this shock, the one who felt the deepest was none other than Qualcomm. As the dominant player in the field of mobile chips, Qualcomm suddenly found itself facing unprecedented challenges. Apple is no longer satisfied with dominating only in the fields of smartphones and tablets, but has extended its tentacles to the PC market - a field that Qualcomm has always wanted to enter but has never succeeded in breaking through. For a long time, Qualcomm's Snapdragon processors have relied on the Cortex series public core provided by Arm. This model was indeed effective in the early development stages of the mobile market: Arm was responsible for providing mature and stable architecture design, while Qualcomm and other vendors focused on system level optimization and integration. This division of labor cooperation has enabled the rapid development of the Android ecosystem and also contributed to Qualcomm's leadership position in the mobile chip field. However, as the demand for mobile computing continues to increase, this pattern of relying on public architecture is beginning to expose significant limitations. Firstly, the degree of differentiation is limited. When everyone uses the same CPU core, the differences between products are mainly reflected in the process technology, frequency tuning, and integration of peripheral components. It is difficult to form the architectural advantages of the core. Secondly, the space for performance optimization is limited, and the public architecture must take into account the needs of all authorized vendors, making it difficult to conduct in-depth optimization for specific application scenarios. The most fatal thing is that the success of Apple's M-series chips has shown the industry the enormous potential of self-developed architectures. Apple has achieved breakthroughs not only in performance, but more importantly, in power consumption control through completely autonomous architecture design. The advantage of integrating software and hardware has put unprecedented pressure on manufacturers who rely on public architecture. Faced with the impact of Apple's M-series chips, the entire industry has begun to rethink its architecture strategy. Intel is striving to advance its hybrid architecture design, AMD is continuously optimizing its Zen series architecture, and within the Arm ecosystem, major vendors are also seeking more autonomy. As a leader in mobile chips, Qualcomm is deeply aware of the urgency of change. There is a consensus within the company that if we continue to rely entirely on Arm's public core, it will not only be difficult to compete with Apple in terms of performance, but more importantly, we will lose our dominant position in the next round of technological competition. Especially in AI computing, edge computing and other emerging fields, the flexibility and optimization space of self-developed architecture will become a decisive advantage. In January 2021, Qualcomm announced its acquisition of Nuvia for $1.3 billion, which caused a huge shock in the industry. For many people, Nuvia is still a relatively unfamiliar name - this two-year-old startup has less than a hundred employees, neither mass-produced products nor mature business models. The valuation of $1.3 billion was indeed astonishing at the time. However, Qualcomm is not interested in the current situation of Nuvia, but in its technological strength and development potential behind it. The founding team of Nuvia can be described as luxurious: CEO Gerard Williams III was once the chief architect of Apple's A-series chips, involved in the design of multiple generations of processors from A7 to A12X; CTO Manu Gulati and Chief System Architect John Bruno also have extensive experience in designing high-performance processors. This team not only deeply participated in the golden age of Apple chips, but more importantly, they have a unique understanding of how to create high-performance low-power processors. Nuvia's technological roadmap is also highly aligned with Qualcomm's strategic goals. This company focuses on the development of high-performance Arm processors for data center and edge computing, and its design philosophy emphasizes to achieve maximum performance output while maintaining low power consumption. Although the company has not been established for a long time, its technical team has demonstrated impressive design capabilities in a short period of time. More importantly, Nuvia has complete self-developed CPU core design capabilities. From optimizing instruction set architecture, to innovating microarchitecture, to developing compilers and software stacks, Nuvia possesses full stack technical capabilities. This is exactly the core capability that Qualcomm urgently needs. After the acquisition, Qualcomm did not rush to quickly productize Nuvia's technology, but chose a more secure strategy of deep integration. The core technology team of Nuvia has been fully integrated into Qualcomm's research and development system, becoming an important component of Qualcomm's CPU design department. This integration is not just about merging personnel, but also a deep integration of technical concepts and design methodologies. During the integration process, Qualcomm demonstrated considerable patience and strategic determination. The company did not rush to launch transitional products, but gave the Nuvia team sufficient time and resources to steadily advance according to the established technology roadmap. At the same time, Qualcomm will also combine its rich experience in the field of mobile chips, including knowledge in power management, thermal design, manufacturing processes, etc., with Nuvia's high-performance design philosophy. On the basis of Nuvia technology, Qualcomm has begun to re plan its high-performance CPU core development roadmap. This is not only a technical adjustment, but also a significant transformation of the entire product strategy. The new development roadmap places greater emphasis on balancing and optimizing performance and power consumption. Drawing on Nuvia's experience in high-performance processor design, Qualcomm has begun exploring more radical architectural innovations, including wider execution units, deeper pipelines, and smarter branch prediction. At the same time, based on Qualcomm's experience in power control in the field of mobile chips, the new architecture design also pays more attention to dynamic power management under different workloads. In terms of application scenarios, the new roadmap also reflects stronger targeting. In addition to traditional mobile applications, emerging scenarios such as PC computing, edge AI, and cloud native applications have become key optimization targets. This multi scenario optimization strategy provides technical support for Qualcomm's expansion in different markets. In 2024, Qualcomm officially released the Oryon CPU core based on Nuvia technology, marking the first significant achievement in the three-year acquisition of Nuvia. The release of Oryon not only marks Qualcomm's official entry into the era of self-developed CPU cores, but more importantly, injects new vitality into the entire Arm ecosystem. From the technical specifications, the Oryon CPU has indeed demonstrated impressive performance. While maintaining relatively low power consumption, Oryon's single core and multi-core performance have reached industry-leading levels. Especially in terms of AI workloads, Oryon has achieved significant performance improvements through specialized optimization design. The impressive performance of the Oryon CPU is attributed to its innovative breakthroughs in multiple technological aspects. These innovations not only demonstrate the technical strength of the Nuvia team, but also showcase Qualcomm's profound expertise in system level optimization. In terms of microarchitecture design, Oryon adopts a wider execution engine and a deeper out of order execution queue, which can better explore instruction level parallelism. Meanwhile, Oryon has made significant progress in reducing memory access latency through improved branch prediction algorithms and a larger cache hierarchy. In terms of power management, Oryon inherits Qualcomm's rich experience in the field of mobile chips. By finely dividing power domains and dynamically adjusting voltage and frequency, Oryon is able to dynamically adjust power consumption based on actual workloads, maximizing battery life while ensuring performance. In terms of AI acceleration, Oryon integrates specialized matrix operation units and vector processing units, which can efficiently execute various machine learning workloads. This hardware acceleration capability provides strong support for Oryon based devices in AI applications. The launch of the Oryon CPU has also opened up new market opportunities for Qualcomm. The Snapdragon X series processors equipped with Oryon directly target the PC market, competing head-on with Intel and AMD's traditional advantage areas. At the same time, Oryon also provides strong technical support for Qualcomm's layout in emerging markets such as edge computing and AI reasoning. The acquisition price of 1.3 billion US dollars did raise many doubts at the time, but now it seems that the strategic value of this investment has been fully reflected. Nuvia not only brought a world-class CPU design team and core technology to Qualcomm, but more importantly, won the initiative in the next round of technology competition. Wi Fi/Bluetooth: The 'invisible wings' behind Atheros Atheros, once a pioneer in wireless communication, has now become a part of the Qualcomm empire, but its technological DNA still quietly flows through billions of devices. From the initial laptop Wi Fi card to the connection module in today's smartphones, Atheros' technological heritage spans the entire development process of wireless communication era. To understand the value of Atheros, we must return to the starting point of wireless communication technology. In 1998, when the Wi Fi standard was just established and most people were still using dial-up internet, Atheros had already keenly perceived the enormous potential of wireless communication. This company, founded by a research team from Stanford University, has been focused from the beginning on a seemingly simple but extremely complex problem: how to achieve efficient and stable wireless connections between devices. In that era, wireless communication technology was still in its very early stages. The 802.11a/b standard has just been released, with a transmission rate of only 11Mbps and limited connection stability. But Atheros engineers saw the infinite possibilities of this technology and began to delve into various technical aspects such as RF design, antenna technology, signal processing algorithms, etc., attempting to break through the technological bottleneck of wireless communication at that time. The first major breakthrough of Atheros came from the deep optimization of OFDM (Orthogonal Frequency Division Multiplexing) technology. Although this technology has great advantages in theory, it faces many challenges in practical applications, including signal synchronization, inter carrier interference, power consumption control, and other issues. Atheros engineers have successfully solved these technical challenges through innovative algorithm design and hardware optimization, laying the foundation for the rapid development of Wi Fi technology in the future. The key to Atheros standing out in the fierce market competition lies in its continuous investment and breakthroughs in technological innovation. The company has established a development strategy of "technology oriented" since its inception, investing a large amount of resources into the research and development of core technologies. After the release of the 802.11g standard, Atheros was the first to launch a chip solution that supports a transmission rate of 54Mbps, far exceeding its competitors at the time. More importantly, Atheros' chips perform well in power control and signal stability, which enables devices using Atheros chips to provide longer battery life and more reliable connection experience. With the introduction of the 802.11n standard, MIMO (Multiple Input Multiple Output) technology has become an important direction for the development of Wi Fi. Atheros has once again demonstrated its technological innovation capabilities by launching the industry's first commercial chips that support MIMO technology. Through the application of multi antenna technology, Atheros' solution not only significantly improves transmission speed, but also significantly enhances signal coverage and anti-interference capability. During this process, Atheros has accumulated a wealth of RF design experience and signal processing technology. The company's engineers have conducted in-depth research on various complex wireless environments, from residential homes to corporate offices, from dense urban environments to open rural areas, and developed corresponding optimization solutions for different application scenarios. With its strong technical capabilities, Atheros has gradually established its position in the market. The company's first significant breakthrough came from the laptop market. In the era when Wi Fi technology was just emerging, laptops were the most important application carriers, and Atheros, with its excellent chip performance and stability, successfully gained the favor of many laptop manufacturers. With the popularization of home broadband, the consumer router market has begun to develop rapidly. Atheros keenly seized this opportunity and launched a chip solution specifically designed for router applications. These chips not only support higher transmission rates, but also have stronger concurrent processing capabilities, which can provide stable connection services for multiple devices simultaneously. In addition to the consumer market, Atheros has also achieved significant success in the field of enterprise wireless communication. Enterprise level applications have more stringent requirements for wireless communication, and Atheros has launched specialized chip solutions for the enterprise market. These products have reached industry-leading levels in RF performance, concurrent processing capabilities, security encryption, and other aspects. Many enterprise network equipment manufacturers have adopted Atheros' chips to build their enterprise level access points (APs) and wireless controller products. Although Atheros initially started with Wi Fi technology, the company quickly realized that the limitations of a single technology were evident in the field of wireless communication. Different application scenarios require different connectivity technologies, and companies that can provide comprehensive connectivity solutions can gain the greatest advantage in market competition. Based on this understanding, Atheros began to expand into the field of Bluetooth technology. Although Bluetooth technology is not as good as Wi Fi in terms of transmission distance and speed, it has unique advantages in low power consumption and point-to-point connections, making it particularly suitable for applications such as audio transmission and input device connections. Atheros' Bluetooth chip solution also demonstrates excellent technical standards. The company's engineers have conducted in-depth research on various levels of the Bluetooth protocol stack, from the lower level RF design to the upper level application protocols, all of which have been deeply optimized. This enables Atheros' Bluetooth chip not only to have better audio transmission quality, but also to support more device connections and richer application functions. With the rise of smartphones and other mobile devices, modular connectivity solutions have become the mainstream demand in the market. Atheros timely launched a Wi Fi/Bluetooth combination chip, integrating the two technologies into a single chip, which not only reduces costs and power consumption, but also simplifies the design complexity of devices. However, at this time, the entire wireless communication market underwent fundamental changes. The requirements for connecting chips in mobile devices are completely different from those in traditional PC products: smaller size, lower power consumption, higher integration, and stricter cost control. This is undoubtedly a huge challenge for Atheros, which is mainly focused on the PC market. Just as Atheros faced challenges in its transition to the mobile age, Qualcomm emerged. In January 2011, Qualcomm announced the acquisition of Atheros for $3.1 billion, which caused a huge shock in the industry. For many observers, this acquisition price seems too high, especially considering the market challenges faced by Atheros at the time. However, Qualcomm's strategic vision was fully reflected in this acquisition. Qualcomm has a deep understanding of the development trend of the mobile Internet era, and recognizes that connectivity technology will become one of the key elements of mobile device competitiveness. Although Qualcomm has taken a dominant position in the cellular communication field, its strength in non cellular connection technologies such as Wi Fi and Bluetooth is relatively limited. The value of Atheros lies not only in its existing products and market position, but more importantly, its profound technical accumulation and experienced engineering team. Qualcomm values Atheros' core capabilities in RF design, signal processing, protocol stack optimization, and other areas, which complement Qualcomm's cellular communication technology perfectly. In addition, Qualcomm has also seen a trend towards the integration of connectivity technologies. In mobile devices, Wi-Fi、 Multiple connectivity technologies such as Bluetooth and cellular communication need to work together, and manufacturers that can provide unified optimization will have significant competitive advantages. By acquiring Atheros, Qualcomm not only gained world-class connectivity technology, but also laid the foundation for its comprehensive layout in the mobile communication field. After the acquisition, Qualcomm did not simply operate Atheros as an independent business unit, but chose a strategy of deep integration. This integration is not only reflected in the technical aspect, but also in the integration of culture and organizational structure. In terms of technology integration, Qualcomm has deeply integrated Atheros' connectivity technology with its own mobile processor technology. This integration is not simply physical splicing, but collaborative optimization at various levels such as architecture design, power management, and signal processing. Through this deep integration, Qualcomm can provide customers with better performance, lower power consumption, and more cost-effective connectivity solutions. In terms of organizational structure, Qualcomm has retained Atheros' core technology team and given them full autonomy to continue technological innovation. At the same time, Qualcomm has organically integrated Atheros engineers with its own R&D team, forming a complete technology chain covering from RF to applications. This deep integration strategy has achieved significant results. The Atheros technology team not only maintains its original innovative vitality, but also gains greater development space on the Qualcomm platform. And Qualcomm has greatly enhanced its strength in the field of connectivity technology through this integration. By acquiring Atheros, Qualcomm has successfully achieved a comprehensive layout in the field of wireless connectivity. Nowadays, Qualcomm is the only company in the world that can simultaneously operate in cellular Wi-Fi、 The company that provides top-level solutions among the three major wireless protocols of Bluetooth. This comprehensive technological capability provides solid support for Qualcomm's dominant position in the mobile communication market. In the smartphone market, almost all mainstream Android devices adopt Qualcomm's connectivity solutions. From the Samsung Galaxy series to Chinese brands such as Xiaomi, OPPO, Vivo, and from high-end flagships to mid to low end products, Qualcomm's connectivity technology is ubiquitous. The achievement of this market coverage is largely attributed to the contribution of Atheros technology. In the PC market, although Intel dominates in processors, Qualcomm also has strong competitiveness in Wi Fi connectivity. Many laptops using Intel processors have chosen Qualcomm's solutions for their Wi Fi modules. In the IoT and smart home markets, Qualcomm's connectivity technology has been widely applied. From smart speakers to smart home appliances, from industrial IoT to smart cities, Qualcomm's connectivity solutions provide reliable technical support for various application scenarios. One of the greatest values of Qualcomm's acquisition of Atheros is the unified optimization of multiple connectivity technologies. In modern mobile devices, cellular Wi-Fi、 Multiple connection technologies such as Bluetooth require collaborative work, while traditional separated designs often lead to issues such as increased power consumption, decreased performance, and poor user experience. By deeply integrating Atheros technology, Qualcomm has achieved unified design and optimization of multi connectivity technology. In the Snapdragon platform, various connectivity technologies share underlying resources such as RF front-end, antenna system, power management, etc., which not only reduces costs and power consumption, but also improves overall performance. If mobile chips are Qualcomm's signature, then connectivity technology is its invisible wing. By acquiring Atheros, Qualcomm not only gained world-class connectivity technology, but more importantly, completed its strategic transformation from a mobile chip manufacturer to a comprehensive communication solution provider. V2X and Vehicle Regulations Blueprint: Autotalks adds the finishing touch In the tide of intelligent driving, the "dialogue" between vehicles is moving from dreams to reality. The communication between vehicles (V2V) and between vehicles and infrastructure (V2I) together form the foundation of V2X (Vehicle to Everything) technology. These 'invisible dialogues' will become a key support for the safety and synergy of autonomous driving, and are a more' far sighted 'warning system than radar and cameras. Qualcomm has long regarded cars as the next highland of mobile Internet. From the Snapdragon Cockpit platform to the Snapdragon Ride positioning autonomous driving control platform, Qualcomm has built a multi-level automotive SoC system covering information entertainment, AI decision-making, sensor fusion, and more. However, what has been missing in this entire solution is the 'last mile' of V2X communication, a key technology. To this end, Qualcomm acquired the Israeli company Autotalks. This company has been deeply involved in the V2X chip field for many years and is one of the few chip manufacturers that can support both DSRC (Dedicated Short Range Communication) and C-V2X (Cellular Connected Vehicle Communication) dual protocols, with customers spread throughout the European and American automotive supply chains. Compared to the slow exploration of self-developed by major manufacturers, Autotalks' technology has been honed and matured through field testing and on-board processes, with the practical advantage of plug and play implementation. In 2023, this acquisition was quickly completed, and Qualcomm thus established a complete link from intelligent cockpit and autonomous driving control to the connection between the vehicle and the outside world. In the Snapdragon Ride platform, Qualcomm has integrated V2X modules natively for the first time, rather than providing them as external chips. This system level integration not only brings about power optimization and cost control, but more importantly, enhances the stability and synergy of V2X in the entire vehicle system, especially opening up new paths in the integration of AI and V2X information at the vehicle end. On a deeper level, this acquisition is not only a 'technological reinforcement', but also a bet on the future intelligent transportation landscape. Driven by 5G, the connection between cars and everything is no longer an isolated system, but an ecosystem of collaborative perception and decision-making. Whoever can occupy a pivotal position in this network holds the discourse power of "swarm intelligence" in autonomous driving. Autotalks is like a finishing touch to Qualcomm. It not only fills a technological gap, but also elevates Qualcomm's "vehicle specification blueprint" from single machine intelligence to collaborative intelligence - from in car intelligent systems to active cognition of the outside environment. This marks another crucial step for Qualcomm from being a "smart car chip supplier" to a "leader in intelligent transportation platforms". SerDes: The behind the scenes player in laying out high-speed interconnectivity If AI chips are powerful "factories" of computing power, then the data flowing between them is the "blood" that maintains the efficient operation of the entire system. What truly determines whether this blood can circulate efficiently is the often overlooked "data highway" - SerDes (serial parallel converter) technology. With the rapid development of AI reasoning, edge computing, automotive electronics and data center, data interconnection capability has become a new bottleneck of SoC system. The delay and bandwidth of data transmission, whether between internal modules of chips or between chips, often directly determine the performance limit of the entire platform. Qualcomm, which has always been known for its expertise in radio frequency and communication, realized early on that high-speed interconnection would be the key infrastructure that would determine the outcome in the process of advancing towards AI and data centers. But this is not Qualcomm's traditional strength. Faced with this "niche but crucial" technological gap, Qualcomm did not choose to develop from scratch, but instead took decisive action and quietly acquired some SerDes assets of Canadian technology company Alphawave Semi. Although not as well-known as some major manufacturers, Alphawave is a star company in the high-performance SerDes IP field, particularly skilled in high-speed interface solutions under various protocol standards such as PCIe, CXL, Ethernet, etc. Its technology enables high-speed transmission of data in a narrow physical channel with low power consumption and low bit error rate, which is crucial for cutting-edge SoC architectures such as processes below 5nm, Chiplet packaging, and multi Die interconnects. Through this acquisition, Qualcomm has quietly completed a "remedial lesson" in its high-speed I/O IP layout. Its strategic significance goes far beyond enhancing the data transmission capabilities of existing SoCs, but also focuses on the "underlying preparation" for Qualcomm's future entry into new battlefields such as data centers, AI acceleration cards, Chiplet heterogeneous computing platforms, etc. Especially in today's Chiplet trend, a single large chip is gradually being replaced by a combination of multiple small chips (Die), and the high-speed interconnection capability between chips has become a watershed for the success or failure of the platform. Without mature SerDes technology, Chiplets are like a puzzle that cannot be pieced together. With Alphawave's technological capabilities, Qualcomm can not only break through the internal "bottlenecks" of SoCs, but also build its own efficient modular platform architecture in the Chiplet era. More importantly, this interconnection capability is no longer limited to "internal optimization". It has become a bridge for Qualcomm to build the next generation of AI and communication fusion systems - whether it is the AI inference card on the server side or the collaborative work of different modules in the vehicle platform, SerDes technology is an irreplaceable "critical channel". In this competition over speed, latency, power consumption, and area, Qualcomm has quietly upgraded itself from a "chip company" to a "system interconnect layout provider" with a precise move. At the critical juncture of transitioning from the era of chips to the era of system integration, SerDes technology, this small screw, is supporting Qualcomm's next round of ambitions. At the end: What I bought is not only technology, but also the future The outside world often says that Qualcomm is a technology company, but in fact, it is more like the best example of capital and technology integration. Each of its core capabilities - graphics CPU、 Wireless communication, V2X, SerDes - almost all originated from strategic mergers and acquisitions. But what truly takes root and sprouts these abilities is Qualcomm's ability to internalize them into an ecosystem and unify them into a platform. It is not simply assembling parts, but melting them into an organic chip empire. This is a story that reached its peak through mergers and acquisitions, but it's not just about buying. It relies on digestion, integration, and re creation. From mobile phones to cars, from connectivity to computing, Qualcomm has made precise attacks time and time again, writing the legendary semiconductor empire that was "bought". As you can see, the foundation of the empire may have been bought, but tall buildings were built brick by brick.

The main feature of GAA nanosheet devices is the vertical stacking of two or more nanosheet conductive channels, with each logic standard cell containing one stack for p-type devices and another stack for n-type devices. This configuration allows designers to further reduce the height of logical standard cells, defined as the number of metal lines (or tracks) per cell multiplied by the metal spacing. Designers can also choose to widen the channel at the expense of sacrificing unit height for larger driving current. In addition to the reduced area, GAA nanosheet transistors have another advantage over FinFETs: the gate surrounds the conductive channel from all directions, enhancing the gate's control over the channel even at shorter channel lengths. Figure 1- TEM image of GAA nanosheet device GAA nanosheet technology is expected to continue for at least three generations before chip manufacturers transition to CFET (complementary FET) technology. Due to its nMOS pMOS vertical stacking structure, the integration complexity of CFET is significantly higher than that of conventional nanosheet devices. According to IMEC's roadmap, the mass production of CFET is only feasible starting from node A7. This means that the era of GAA nanosheets must extend at least to the A10 technology node, where the unit height is expected to be as small as 90 nanometers. However, reducing the standard cell size based on GAA nanosheets without affecting performance is extremely challenging. This is exactly where forksheet device architecture may bring relief, as it is a non-destructive technology with greater scalability potential than conventional GAA nanosheet technology. Forksheet, 1nm reliance In 2017, IMEC launched the forksheet device architecture, first as a scaling booster for SRAM cells, and later as a scaling enabler for logic standard cells. The unique feature of its first implementation is the placement of a dielectric wall between nMOS and pMOS devices before gate patterning. Due to the fact that this wall is located in the middle of the logical standard unit, the architecture is referred to as an "inner wall" fork sheet. The wall physically isolates the p-gate trench from the n-gate trench, achieving a tighter n-to-p spacing than FinFET or nanosheet devices. This allows for further reduction of unit area (unit height up to 90nm) while still providing performance improvement. In this' inner wall 'configuration, these thin sheets are controlled by a tri gate forked structure, hence the name of the device. Figure 2- TEM image of the inner wall fork device At VLSI 2021, imec demonstrated the manufacturability of the 300mm inner wall fork sheet process flow. Conducting electrical characteristic tests on fully functional devices confirms that forksheet is the most promising device architecture, capable of extending the miniaturized roadmap of logic and SRAM nanosheets to the A10 node. Due to the reuse of most of the production steps of nanosheets in the integrated process, the technological evolution from nanosheets to forksheets can be considered non disruptive. Manufacturability is being challenged Despite the successful hardware demonstration, some concerns about manufacturability still exist, which has led IMEC to reconsider and improve its initial fork sheet device architecture. The main challenge is related to the manufacturability of the inner wall itself. In order to achieve a 90nm logic standard cell height, the dielectric wall needs to be very thin, within the range of 8-10nm. However, due to the early manufacturing of the equipment process, the wall will be exposed to all subsequent front-end process (FEOL) etching steps, which may further reduce the thickness of the wall, placing considerable demands on the selection of wall materials. In addition, in order to achieve process steps specific to n or p (such as p/n source/drain epitaxy), dedicated masks must be precisely placed on thin dielectric walls, which poses a challenge to the alignment of p/n masks. In addition, 90% of devices in practical applications have a common gate for n and p channels. In standard cells with inner wall forksheet devices, dielectric walls can hinder the pn connection gate. Unless the gate is made higher to cross the wall, which would increase parasitic capacitance. Finally, chip manufacturers are concerned about the three gate architecture, as the gate only surrounds the channel from three sides. Compared with the GAA structure, there is a risk of losing control over the channel at the gate, especially when the channel length is short. External wall fork: dielectric wall at the boundary of CELL At the Very Large Scale Integration Technology and Circuit Symposium 2025 (VLSI 2025), researchers from imec presented a novel fork sheet device architecture and named it the "outer wall fork sheet". They demonstrated through TCAD simulation how this outer wall forksheet improves its previous design by reducing process complexity, providing excellent performance, and maintaining area scalability. Figure 3- Imec's logical technology roadmap, showing the extension of the nanosheet era from 2nm to A10 node, using outer wall forksheet, and then transitioning to A7 and higher versions of CFET The outer wall forksheet places the dielectric wall at the boundary of the standard cell, making it a pp or nn wall. This allows each wall to be shared with adjacent standard cells and can be thickened (up to about 15 nanometers) without affecting the height of the 90 nanometer cells. Another significant feature is the wall cast integration method. The entire process begins with the formation of a wide Si/SiGe stack - a step that is repeated in any GAA technology. After etching away SiGe in the nanosheet channel release step, the stacked Si layer will form nanosheet shaped conductive channels. The dielectric wall will eventually divide the stack into two, with two FETs of similar polarity located on either side of the wall. The dielectric wall itself is processed towards the end of the integration process, that is, after the channel release of the nanosheets, source/drain etching, and source/drain epitaxial growth. The step of replacing the metal gate (RMG) has completed the integration process. Figure 4- Schematic diagram of the forksheet structure for the (top) inner wall and (bottom) outer wall 5 key improvements to the outer wall forksheet Compared with GAA nanosheet devices, inner and outer wall forksheets have two common advantages. In terms of area scaling, they are all able to achieve a 90nm logical standard cell height at the A10 node, which is more advantageous compared to the 115nm cell height in A14 nanosheet technology. The second common advantage is the reduction of parasitic capacitance: the two field-effect transistors (FETs) located on both sides of the wall (with n and p on the inner wall and n and n/or p and p on the outer wall) can be placed closer than units based on nanosheets without causing capacitance problems. In addition, the outer wall forks are expected to surpass the inner wall forks in five key aspects of design. Firstly, due to the adoption of the wall last integration method, the dielectric wall eliminates several complex FEOL steps. Therefore, it can be made from mainstream silica. In the back wall process step, walls are formed by forming trenches in a wide Si/SiGe stack and filling them with SiO2 dielectric. Secondly, as the wall is located at the boundary of the unit, its width can be relaxed to about 15nm, thereby simplifying the process. Thirdly, it is now easy to connect the gates of n and p devices within a standard cell without passing through dielectric walls. Fourthly, the outer wall forksheets are expected to provide better gate control than the inner wall devices, which is related to their ability to form Ω - gate structures instead of three gate forksheets. A wider dielectric wall makes it possible to etch the wall several nanometers in the final RMG step. This allows the gate to partially surround the fourth edge of the channel, forming a W-shaped gate and enhancing control over the channel. Through TCAD simulation, imec researchers found that etching off the 5-nanometer dielectric wall is the best choice, which can increase the driving current by about 25%. Figure 5- The effect of wall etching on gate formation: from triple gate to Ω gate, and then to GAA The fifth aspect is related to the potential of forksheet integrated flow to provide full channel strain, which is an additional performance improvement that is beneficial for driving current. Usually, full channel strain can be obtained by implementing source/drain stress sources. This method has been proven to be highly effective in (p-type) FinFETs, but it is difficult to implement in GAA nanosheets and inner wall forksheet device architectures. Conceptually, the idea is to incorporate Ge atoms into the source/drain regions. Due to the larger size of Ge atoms compared to Si atoms, they introduce compressive strain in the Si channel, thereby increasing the mobility of charge carriers. Figure 6- At the beginning of the outer wall fork sheet process, a "pre all" hard mask (brown) is deposited on top of a wide Si (gray)/SiGe (purple) layer stack. In this way, the Si "seed crystal" beneath the hard mask can support epitaxial growth of the source/drain electrodes The reason why the outer wall forksheet device can achieve fully effective source/drain stress sources is because it adopts the wall last method. Before making the wall, the hard mask will continue to cover the middle portion of the wide Si/SiGe stack, which will later be used to form the wall (Figure 6). The 'Si spine' beneath this hard mask can now serve as a seed crystal during source/drain epitaxial growth, acting as a silicon 'template' that extends from one gate channel to the next. This is similar to Si subfin in FinFET technology: imagine rotating the source/drain epitaxial module 90 ° (Figure 7). If there is no such silicon crystal template, vertical defects will form at the source/drain epitaxial interface, thereby eliminating the compressive strain formed in the silicon channel. Figure 7- The Si spine (right) in the outer wall fork sheet provides a continuous silicon crystal template from one gate channel to the next. This is conceptually similar to Si subfin in FinFET technology (left) External wall forksheet in SRAM and ring oscillator design Finally, IMEC conducted a benchmark study to quantify the power performance area (PPA) advantage of the outer wall fork sheet. When comparing the area of the A10 outer wall fork sheet and the SRAM bit cell based on A14 nanosheets, the area advantage of the nanosheet architecture becomes apparent. Layout display shows that the SRAM cell area based on the outer wall fork sheet has decreased by 22%, due to the reduction in the spacing between pp and nn on the basis of the reduction in gate spacing. Another key indicator for performance evaluation is the simulated frequency of the ring oscillator, expressed as the ratio of effective driving current to effective capacitance (I eff/C eff). Simulation shows that for node A10, an outer wall fork is required to maintain frequency consistency with the previous A14 and 2nm nodes, provided that all of these device structures can achieve full channel stress. It has been proven that achieving full channel stress in nanosheets (2nm and A14) and inner wall fork sheet devices is challenging, and its absence results in a drive current loss of approximately 33%. Therefore, it is expected that the ability to implement an effective source/drain stressor in the outer wall fork sheet device will result in further performance advantages in the design of ring oscillators. Figure 8- Simulation results of ring oscillator (with and without backend (BEOL) load) Outlook and Conclusion The fork blade device architecture was introduced by IMEC with the aim of extending the logic technology roadmap based on nanosheets to the A10 technology node and expecting CFET to achieve mass production. Due to manufacturability issues, IMEC abandoned the original inner wall fork design and developed an "upgraded" version: outer wall fork design. Compared to the inner wall fork sheet, the new design ensures higher manufacturability while improving performance and reducing surface area. Looking ahead to the future, IMEC is currently researching the compatibility between the outer wall forkfoot design and the CFET architecture, as well as to what extent CFET can benefit from PPA from this innovative expansion booster.