In the battlefield of wafer foundry without gunpowder, every iteration of advanced processes touches the nerves of the global technology community. Nowadays, this competition has entered the era of 1.4nm: high research and development costs and strict technological barriers are pushing Moore's Law to its true limits. However, as the semiconductor industry rises to a national strategic level, price is no longer the only consideration. By the way, 1.4nm is often written as 14 A (A=0.1 nm), but node names such as 3nm, 2nm, and even 1.4nm are now more of a "banner" to distinguish between new and old processes, and have long been disconnected from the physical size of actual transistors.
As the three major players in the 1.4nm race, TSMC, Intel, and Samsung can be regarded as a large-scale "Three Kingdoms", each laying out their own strategies in the game of performance and technology. However, under the interweaving of multiple pressures such as yield, production capacity, diversified customer demands, and economic investment, this global technology competition among top companies is quietly emerging with differences and variables.
Samsung 1.4nm Delay
Samsung Electronics, which was originally ambitious, officially announced at the "SAFE Forum 2025" on June 1st that its 1.4nm (14A) semiconductor production target will be postponed to 2029, two years later than previously planned. The construction of the 1.4nm testing line originally scheduled to start in the second quarter of this year has also been postponed, and the investment plan has been postponed until the end of this year or the first half of next year. This is not only one year later than TSMC's 2028 target, but also raises industry concerns about a series of deep-seated issues in Samsung's wafer foundry division. Now, Samsung is one step further away from its dream of becoming the "top semiconductor foundry" by 2030.
Why is there a delay? It is widely interpreted that this is Samsung Foundry's strategic move to cope with the current loss situation. It is reported that Samsung's wafer foundry division suffered losses of up to 4 trillion Korean won last year due to the loss of major customers; And in the first quarter of this year, the loss also reached an astonishing 2 trillion Korean won. Faced with performance pressure, Samsung Electronics has decided to focus on immediate process improvements rather than investing heavily in advanced technology.
Therefore, Samsung is trying to improve its profitability by increasing the maturity and utilization rate of 2nm or higher processes. Instead of blindly pursuing advanced processes, it is better to first improve the yield of its mass production processes. According to insiders, the manufacturing yield of Samsung's 2nm process is currently about 40%, while TSMC has exceeded 60%, reaching the threshold for stable mass production. It is reported that the 2nm (SF2) process is scheduled for mass production this year as originally planned, with a focus on stabilizing and improving SF2P (second-generation) and SF2X (third-generation) technologies before 2028; At the same time, profitability can be ensured by increasing the operational efficiency of relatively mature processes such as 4nm, 5nm, and 8nm. There are even reports that Samsung has requested its partners to focus on developing relevant IPs to enhance the attractiveness of these processes.
In order to ensure the smooth mass production of the Exynos 2600 application processor using a 2nm process, which will be released in the second half of the year, Samsung's Chief Technology Officer (CTO), Nan Xiyu, is personally forming and operating the 2nm Task Force (TF) team. After all, if the yield continues to remain at a low level of 20-30%, even domestic chips cannot guarantee supply. In addition, striving for 2nm orders from large North American technology companies such as Tesla and Qualcomm is also a key factor for Samsung to increase revenue in the future.
According to a report by the Central Times, a semiconductor industry source said, "Samsung Electronics' foundries have been focused on competing at cutting-edge nodes, repeatedly entering the next generation of processes under unstable conditions, resulting in a decrease in yield and loss of customer trust. The decision to strengthen the strength of foundries can be seen as a positive measure
Intel changes bet on 14A, 18A, where do we go from here
On the other hand, Intel's wafer foundry division is also struggling. Recently, Reuters reported that Intel CEO Chen Liwu is considering shifting the focus of wafer foundry to the "14A" chip manufacturing process, while the "18A" process promoted by former CEO Kissinger may face the risk of being cancelled or reduced in priority.
18A was once a "generational leap" for advanced technologies such as RibbonFET and PowerVia, and Intel had high hopes for it. PowerVia is Intel's unique and industry-leading backside power architecture, which can increase standard cell utilization by 5-10% and improve ISO power performance by up to 4%. RibbonFET is a ring gate (GAA) transistor implemented by Intel's foundry, which improves density and performance compared to FinFET. ）Reuters reported that Intel's 18A process is considered to be at the same level as TSMC's 3-nanometer process.
Schematic diagram of RibbonFET and PowerVia (source: Intel)
Why is there such a change?
The customer appeal of 18A is insufficient: Although 18A has won customers such as Amazon and Microsoft, it was initially designed more for Intel's own products, with the goal of increasing production of its "Panther Lake" laptop chips by later 2025. For Intel, which urgently needs to win more external OEM customers such as Apple and Nvidia, the appeal of the 18A seems insufficient.
The OEM business urgently needs a breakthrough: Intel's OEM department urgently needs customer orders. Instead of stubbornly fighting on the already "late" 18A, it is better to invest more resources into the more promising 14A process.
Financial considerations: The development of 18A has cost billions of dollars, and if the focus is cancelled or reduced, it may result in losses of hundreds of millions of dollars. But in the rapidly changing market, timely stop loss and adjust strategy may be a wiser choice.
According to the original plan, Intel's 18A derivative version 18A-P will be released in 2026, and 18A-PT will be released in 2028. According to Wccftech, 18A-PT is particularly noteworthy as it will become Intel's first node to support Foveros Direct 3D hybrid bonding, enabling it to adopt TSMC's advanced interconnect technology.
Chen Liwu believes that if Intel wants to compete with TSMC, it can only have an advantage in the 14A process. As early as February last year, Intel included the 14A-E in its advanced process schedule and announced at this year's "Intel Foundry Direct Connect 2025" that it would undergo risk trial production in 2027, with its derivative version 14A-E also planned to be produced in the same year. If this shift in focus comes true, it will be the second consecutive node for Intel to lower its priority, and it is more likely to mean that Intel will "substantially withdraw" from the OEM market in the coming years, with serious consequences.
Technically speaking, the Intel 14A will go further than the 18A by adopting the second-generation surround gate technology RibbonFET 2 and the second-generation back power supply network PowerDirect. In addition, the 14A also uses enhanced cell technology Turbo Cells, which can further improve speed (including CPU maximum frequency and GPU critical path) when used in conjunction with RibbonFET 2. Turbo Cells allow designers to optimize higher performance units and more energy-efficient unit combinations within the design module, achieving a balance between power consumption, performance, and area for the target application. Compared to its predecessor, the performance of the 14A has improved by 15% to 20%, chip density has increased by nearly 30%, and power consumption is expected to decrease by more than 25%.
It is worth mentioning that Intel is at the forefront of adopting High NA EUV (high numerical aperture extreme ultraviolet lithography equipment) and has installed a second High NA EUV in Oregon. Intel emphasizes that the 14A is compatible with Low or High NA solutions and has no impact on customer design rules.
Despite its strong technological capabilities, Intel still faces numerous obstacles. Competitors such as TSMC and Samsung are actively expanding their own processes, while Intel's annual capital expenditure of over $40 billion to maintain its leading position may strain its balance sheet. The release schedule of the 14A process node in 2026 also depends on whether the yield problem of high numerical aperture EUV lithography machines can be solved. Given ASML's limited supply of such lithography machines, this task is very complex.
In addition, the timeline adopted by the client is still uncertain. Although Microsoft's 18A chip is progressing smoothly, major AI companies such as Nvidia and AMD still heavily rely on TSMC. Intel's success depends on whether these companies can believe that its nodes can provide excellent PPAC (power consumption, performance, area, cost) metrics - a statement that must be proven through mass production.
Anyway, Intel's 14A/18A roadmap represents its best opportunity to regain leadership in the semiconductor manufacturing industry. Intel can only take a gamble.
TSMC steadily operates at 1.4nm
As an industry leader, TSMC is the most highly anticipated company to take the lead in 1.4nm. After all, TSMC has demonstrated strong advantages in previous generations of nodes. For example, although Samsung was earlier than TSMC in 3nm, its yield rate was not as good as TSMC's. 3nm did not win more customers for Samsung, but instead lost them. It has been proven that 'the first to submit the paper may not necessarily be the best answer.' For the wafer foundry industry, true leadership lies in mature technology and stable mass production capabilities.
A14 is TSMC's second-generation nanosheet transistor, which is considered a full node (PPA) compared to N2. A14 also adopts the innovative standard cell architecture of "NanoFlex Pro" to achieve better performance, energy efficiency, and design flexibility. Speed increases by 10-15% at the same power, power consumption decreases by 25-30% at the same speed, and logic density increases by 1.2 times.
TSMC expects A14 to be put into production in 2028, and the development is progressing smoothly with yield achieved ahead of schedule.
It is interesting that TSMC has always maintained a relatively cautious and conservative attitude towards the adoption of new technologies in the research and development of new nodes. The reason is that once multiple new technologies that have not been fully validated and have high risk boundaries are introduced into the process, the "ramp up" period of the yield curve will be significantly prolonged, thereby slowing down the overall speed from trial production to mass production. TSMC's conservative strategy can precisely strike a balance between immature new technologies and large-scale delivery demands, shorten the risk trial production cycle, and quickly seize market share.
Specifically, let's take a look:
Cost benefit trade-off: The single procurement and maintenance cost of High NA EUV lithography machines is almost 2.5 times higher than that of ordinary NA EUV, requiring additional process debugging and supporting material investment, significantly increasing wafer costs. For A14 chips aimed at the mass consumer market, once High NA EUV is adopted, it will not only cause a sharp increase in manufacturing costs and difficulty in compressing the overall BOM, but may also affect OEM manufacturers' procurement decisions due to high premiums.
Yield ramp up and stable delivery: Before sufficient yield validation and controllable risks are achieved for ordinary NA EUV equipment and related supporting facilities, hasty switching can prolong the time window for yield improvement and even lead to delivery delays. TSMC initially did not introduce Backside Power Delivery and Super Power Rail (SPR) on its first generation products such as A14 and N2. After the downstream design toolchain and material ecology are further improved, TSMC will gradually introduce them at improvement nodes such as A16 and A14P to ensure the delivery rhythm of the mainstream market.
Targeted by customer group and market positioning: For mainstream nodes such as A14, which are aimed at high-end smartphones and consumer electronics, cost-effectiveness often takes priority over extreme performance; Enhanced processes such as A14P and A16 are more targeted towards servers, AI acceleration cards, and other fields that are extremely sensitive to performance and power consumption and willing to pay a premium. Between technological maturity and market demand, TSMC has achieved the maximization of commercial value through differentiated layout, striving for progress while maintaining stability.
Although Zhang Xiaoqiang, Senior Vice President of Business Development at TSMC, has pointed out that High NA EUV has significant value in terms of 1.5D/2D design freedom, process step simplification, and capacity improvement in the field of logic chips (which can bring about a cost-effectiveness increase of about 35%), TSMC is not in a hurry to introduce all cutting-edge technologies into mainstream nodes at once from 2nm to A14 processes. Instead, it chooses to gradually adopt High NA EUV in the A14P process that can afford the cost premium in the future. This not only ensures the controllable cost and stable delivery of mainstream products, but also provides sufficient technical support for higher end applications.
summarize
According to the timeline, the production of Intel 14A will be in 2027, TSMC in 2028, and Samsung in 2029. In terms of the adoption of High NA EUV lithography machines, Intel is the "first person to eat the crab", TSMC is slightly cautious, and Samsung has not clearly stated whether to use them, only stating that it is evaluating the possibility of using high NA EUV tools in its 1.4nm foundry process.
This 1.4nm competition is not only a competition of technological strength, but also a comprehensive consideration of strategic decision-making, market positioning, and profitability. Who can stand out in this advanced process of the "Three Kingdoms"? Let's wait and see!
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